Jörg Brakensiek

Virtualization as an enabler for security in mobile devices

Virtualization, a well established technology in the desktop and server domain, is currently investigated and analyzed with respect to its potential within mobile devices. The paper argues that mobile devices, which are targeting a completely open setup (e.g. Linux based), are facing severe security challenges. Thus, virtualization will be discussed as an enabler for security in mobile devices. Virtualization approaches and elements are discussed in detail taking this use case and existing limitations of mobile embedded devices into account.

Terminal mode: transforming mobile devices into automotive application platforms

Mobile devices such as smart phones have enabled consumers to gain access to a growing number of interactive and useful applications, anytime anywhere. However, once a user enters his/her vehicle the availability of such applications and their user experience degrades drastically -- either because of being restricted to using the few applications available on the In-Vehicle Infotainment (IVI) system or due to the challenges of interacting with a tiny mobile device screen attached to a car dock. In this paper, we present Terminal Mode -- a technology which transforms mobile devices into automotive application platforms and seamlessly integrates them into vehicle infotainment systems. This technology not only enables consumers to access their favorite mobile services and applications in a safe manner while traveling in a vehicle but also provides top quality user experience consistent with high-end IVI systems.

Morphing Smartphones into Automotive Application Platforms

The Terminal Mode technology integrates smartphones into in-vehicle infotainment systems and transforms them into automotive application platforms on the fly, allowing drivers to safely access and interact with mobile applications.

Re-configurable multi-standard terminal for heterogeneous networks

The next generation of mobile communication systems will lead to an integration of existing networks and access technologies, forming a heterogeneous network. New architectures are needed to serve new requirements from these new systems. The paper highlights the requirements of a reconfigurable multi-standard terminal from the physical-layer point of view. A reconfigurable architecture consisting of algorithm domain specific accelerators, allowing autonomous complex digital signal processing without interference from a microprocessor or digital signal processor, is explained. Performance comparison numbers with the latest digital signal processors show the effectiveness of the proposed architecture.

Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures

In this contribution the concept of functional- level power analysis (FLPA) for power estimation of programmable processors is extended in order to model embedded as well as heterogeneous processor architectures featuring different embedded processor cores. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like, e.g. processing unit, clock network, internal memory, etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional-level and instruction-level (FLPA/ILPA) model in order to achieve a good modeling accuracy. In order to show the applicability of this approach even a heterogeneous processor architecture (OMAP5912) featuring an ARM926EJ-S core and a C55x DSP core has been modeled using the hybrid FLPA/ILPA technique described before. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders or classical benchmark suits. Estimated power figures for the inspected tasks are compared to physically measured values for both inspected processor architectures. A resulting maximum estimation error of 9% for the ARM940T and less than 4% for the OMAP5912 is achieved.

Software radio approach for re-configurable multi-standard radios

Next generation wireless systems will lead to an integration of existing networks, forming a heterogeneous network. Re-configurable systems will be the enabling technology sharing hardware resources for different purposes. This paper highlights the requirements of a reconfigurable multi-standard terminal from the physical-layer point of view. A re-configurable architecture consisting of algorithm domain specific accelerators, allowing autonomous complex digital signal processing without interference from a microprocessor, is explained. Performance comparison numbers with latest digital signal processors shows the effectiveness of the proposed architecture.

OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis

In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For parallelization issues the OpenMP programming model has been used which can be efficiently applied on C-level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.

Hybrid functional and instruction level power modeling for embedded processors

In this contribution the concept of Functional-Level Power Analysis (FLPA) for power estimation of programmable processors is extended in order to model even embedded general purpose processors. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional level and instruction level model in order to achieve a good modeling accuracy. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders. Estimated power figures for the inspected tasks are compared to physically measured values. A resulting maximum estimation error of less than 8 % is achieved.

Device Driver Isolation within Virtualized Embedded Platforms

Mobile device manufacturers are facing the challenge, to maintain device drivers across an increasing number of product variants. Isolation of device drivers into a separate domain using virtualization technology offers a way out of the resulting porting dilemma. This paper explains the architecture concept based on the L4/Fiasco microkernel, using an exemplary block device. The paper specifically details challenges and solutions with respect to enabling DMA access and ensuring access protection in the virtualized environment. Benchmark results are given to show the performance impact of the chosen architecture.

Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform

In this contribution, the potential of parallelized software that implements algorithms of digital signal processing on a multicore processor platform is analyzed. For this purpose various digital signal processing tasks have been implemented on a prototyping platform i.e. an ARM MPCore featuring four ARM 11 processor cores. In order to analyze the effect of parallelization on the resulting performance-power ratio, influencing parameters like e.g. the number of issued program threads have been studied. For paralllelization issues the OpenMP programming model has been used which can be efficiently applied on C- level. In order to elaborate power efficient code also a functional and instruction level power model of the MPCore has been derived which features a high estimation accuracy. Using this power model and exploiting the capabilities of OpenMP a variety of exemplary tasks could be efficiently parallelized. The general efficiency potential of parallelization for multiprocessor architectures can be assembled.