Jorge Kittl

10×10nm 2 Hf/HfO x crossbar resistive RAM with excellent performance, reliability and low-energy operation

We report on worlds smallest HfO2-based Resistive RAM (RRAM) cell to date, featuring a novel Hf/HfOx resistive element stack, with an area of less than 10×10 nm2, fast ns-range on/off switching times at low-voltages and with a switching energy per bit of <0.1pJ. With excellent endurance of more than 5.107cycles, large on/off verified-window (>50), no closure of the on/off window after 30hrs/200C and failure-free device operation after 30hrs/250C thermal stress, the major device-level nonvolatile memory requirements are met. Furthermore, we clarify the impact of film crystallinity on cell operation from a scalability viewpoint, the role of the cap layer and bring insight into the switching mechanisms.

Kinetics and nucleation model of the C49 to C54 phase transformation in TiSi2 thin films on deep‐sub‐micron n+ type polycrystalline silicon lines

A detailed kinetic study of the C49 to C54 phase transformation in TiSi2 thin films was performed, to obtain the full time, temperature, and linewidth dependence of the fraction transformed during rapid thermal annealing on patterned deep‐sub‐micron lines. A Johnson–Mehl–Avrami kinetic analysis showed Avrami exponents of 0.8±0.2 for all submicron lines and 1.9±0.2 for a 40 μm side square structure. The activation energy of 3.9 eV was independent of linewidth. Transformation times increased dramatically as linewidth decreased. A kinetic model based on the density of nucleation sites as a function of linewidth and C49 grain size is proposed and shown to fit the data.

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co-Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co-Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni2Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of ∼ 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi2 at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.

Balancing SET/RESET Pulse for

By tuning the SET/RESET pulse amplitude conditions, the pulse endurance of our 40-nm HfO2/Hf 1T1R resistive-random-access-memory devices demonstrates varying failure behaviors after 106 cycles. For unbalanced SET/RESET pulse amplitude conditions, both low-resistance state (LRS) and high-resistance state (HRS) failures may occur, while varying the pulsewidths influences the LRS/HRS window and the stability of the LRS/HRS states. The failure of the HRS or LRS state during cycling is ascribed to the depletion or excess of oxygen vacancies at the switching interface. Through a dc SET/RESET recovery operation, LRS/HRS states can be recovered after failure, indicating that the distribution of oxygen vacancies can be restored. By optimally balancing the SET/RESET pulse conditions, more than 1010 pulse endurance cycles is achieved.

>\hbox{10}^{10}

Vanadium dioxide (VO2) has the interesting feature that it undergoes a reversible semiconductor-metal transition (SMT) when the temperature is varied near its transition temperature at 68°C.1 The variation in optical constants makes VO2 useful as a coating material for e.g. thermochromic windows,2 while the associated change in resistivity could be interesting for applications in microelectronics, e.g. for resistive switches and memories.3 Due to aggressive scaling and increasing integration complexity, atomic layer deposition (ALD) is gaining importance for depositing oxides in microelectronics. However, attempts to deposit VO2 by ALD result in most cases in the undesirable V2O5. In the present work, we demonstrate the growth of VO2 by using Tetrakis[EthylMethylAmino]Vanadium and ozone in an ALD process at only 150°C. XPS reveals a 4+ oxidation state for the vanadium, related to VO2. Films deposited on SiO2 are amorphous, but during a thermal treatment in inert gas at 450°C VO2(R) is formed as the first and only crystalline phase. The semiconductor-metal transition has been observed both with in-situ X-ray diffraction and resistivity measurements. Near a temperature of 67°C, the crystal structure changes from VO2(M1) below the transition temperature to VO2(R) above with a hysteresis of 12°C. Correlated to this phase change, the resistivity varies over more than 2 orders of magnitude.

Endurance in

A complete determination of the effective work functions (WF) of NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si on HfSiON and on SiO/sub 2/ is presented. Conditions for formation of fully silicided (FUSI) gates for NiSi/sub 2/, NiSi, Ni/sub 3/Si/sub 2/, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si crystalline phases were identified. A double thickness series (HfSiON/SiO/sub 2/) was used to extract WF on HfSiON accounting for charge effects. A strong effect on WF of Ni content is observed for HfSiON, with higher WF for the Ni-rich silicides suggesting unpinning of the Fermi level. A mild dependence is observed for SiO/sub 2/. While all Ni-rich silicides have adequate WF for pMOS applications, Ni/sub 2/Si is most attractive due to its low formation temperature, lower volume expansion and ease of integration. Similar threshold voltages (-0.3 V) were obtained on Ni/sub 2/Si and Ni/sub 31/Si/sub 12/ FUSI HfSiON pMOSFETS.

\hbox{HfO}_{2}\hbox{/Hf}

An analytic dynamic hour glass model for HfO2 RRAM is demonstrated, describing the reset as a dynamic equilibrium process and the set as a constriction growth limited by ion mobility and current compliance. The dependence on time, voltage and forming conditions is in good constriction growth agreement with experiments. Since the model is fully analytical, it can be implemented in a circuit simulator.

1T1R Bipolar RRAM

Abstract An overview of the development of advanced Ti and Co self-aligned silicide (SALICIDE) processes for deep-sub micron high performance CMOS technologies at Texas Instruments is presented. SALICIDES are a key factor for scaling of high-performance CMOS devices. They are used to lower sheet resistance of gate and source/drain regions, contact resistance and source/drain series resistance, increasing device performance and lowering RC delays to allow faster operation. Their applicability to deep-sub-micron technologies is determined by the fundamental materials aspects controlling silicide phase formation and evolution, as well as process integration issues such as effect of subsequent processing steps on the silicide films or effects of silicide related process steps on transistor characteristics. The main scaling issues for conventional processes, high resistivity on narrow lines for Ti SALICIDE and high diode leakage on shallow junctions for Co SALICIDE, are addressed. Detailed kinetic studies of the high resistivity to low resistivity phase transformations (TiSi2 C49 to C54 and CoSi to CoSi2) and their dependence on linewidth and film thickness are presented. A nucleation density model is shown to account for the measured linewidth dependence and effect of pre-amorphization implants on the TiSi2 C49 to C54 transformation and explain, as a result, narrow line sheet resistance. This overview covers studies on rapid thermal processing (RTP) for Ti and for Co SALICIDE, pre-amorphization implants and Mo impurities which allowed the first demonstration of low resistivity Ti SALICIDE at 0.10 μm gate lengths, as well as applications to sub-0.18 μm CMOS technologies and integration issues.

Semiconductor-metal transition in thin VO2 films grown by ozone based atomic layer deposition

Strontium titanate (STO) is a promising candidate as a high-k dielectric for dynamic random access memory application. STO thin films are deposited by atomic layer deposition using Sr( t Bu 3 Cp) 2 , Ti(OMe) 4 , and H 2 O as precursors. Growth and saturation behavior of STO and binary oxides are evaluated by ellipsometry thickness measurements. The precursor pulse ratio controls the amount of Sr and Ti incorporated in STO films. Stoichiometric SrTiO 3 is characterized by the lowest crystallization temperature and largest refractive index, density, and dielectric constant. An excess of Ti or Sr results in an increase in the crystallization onset temperature and contraction or expansion of the cubic cell constant of perovskite SrTiO 3 . Incorporation of more Sr in STO reduces the leakage current density but also increases the capacitance-equivalent thickness.

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

In this letter, we explore the influence of the CuxTe1-x layer composition (0.2   0.7 leads to large reset power, similar to pure-Cu electrodes, x < 0.3 results in volatile forming properties. The intermediate range 0.5 < x < 0.7 shows optimum memory properties, featuring improved control of filament programming using <5 μA as well as state stability at 85 °C. The composition-dependent programming control and filament stability are closely associated with the phases in the CuxTe1−x layer and are explained as related to the chemical affinity between Cu and Te.