Jörn Schneider

Cache and pipeline sensitive fixed priority scheduling for preemptive real-time systems

Current schedulability analyses for preemptive systems consider cache behaviour by adding preemption-caused cache reload costs. Thereby, they ignore the fact that delays due to cache misses often have a reduced impact because of pipeline effects. In this paper, these methods are called isolated. Pipeline-related preemption costs are not considered at all in current schedulability analyses. This paper presents two cache- and pipeline-sensitive response time analysis methods for fixed-priority preemptive scheduling. The first is an isolated method. The second method incorporates the preemption-caused cache costs into the worst-case execution time (WCET) of the preempted task. This allows for the compensation of delays due to cache misses by pipeline effects. It is shown that the applicability of isolated approaches is limited to a certain class of CPUs. Practical experiments are used to compare both methods.

Run-Time Guarantees for Real-Time Systems—The USES Approach

The USES group follows an approach to compute reliable runtime guarantees which is based on well-understood theoretical foundations, practical in use, and efficient.

Pipeline behavior prediction for superscalar processors

For real time systems not only the logical function is important but also the timing behavior, i. e. hard real time systems must react inside their deadlines. To guarantee this it is necessary to know upper bounds for the worst case execution times (WOETs). The accuracy of the prediction of WOETs depends strongly on the ability to model the features of the target processor. Cache memories, pipelines and parallel functional units are microarchitectural components which are responsible for the speed gain of modern processors. It is not trivial to determine their influence when predicting the worst case execution time of programs. This report describes a method to predict the behavior of piplined superscalar processors and an implementation of this approach for the SuperSPARC I microprocessor. The results of a preceding cache behavior prediction is taken into account. The method uses static program analysis. The implementation has been realized using the PAG (Program Analyzer Generator) tool. The approach is independent of the source language as it works directly on the instruction level.

Overcoming the Interoperability Barrier in Mixed-Criticality Systems

Concurrent engineering of system parts with diverging requirements can be extremely challenging. One example are mixed-criticality systems that integrate hard real-time software for safety–critical functionality and general purpose software providing a sophisticated user interface. The automotive industry, as well as other industrial branches, has a growing need to integrate consumer electronics applications (e.g. Linux based) and safety-relevant applications requiring an underlying hard real-time operating system. Some established concepts for mixed-criticality systems can be found in the avionics domain. This paper demonstrates that the principles behind these concepts are a dead end regarding innovations requiring a close interoperation. The second contribution of the paper is to present a different solution approach as a potential remedy that allows the different developer groups (hard real-time and standard IT) to retain their attitude to software development. The core of the novel approach is a worst-case execution time (WCET) directed OS service, which could serve as solution pattern for further problems in mixed-criticality systems.

Towards an evaluation infrastructure for automotive multicore real-time operating systems

The automotive industry is on the road to multicore and already included supporting features in their AUTOSAR standard, yet they could not decide for a multicore resource locking protocol. It is crucial for the future acceptance and possibilities of multicore systems to allow for informed decisions on this topic, as it immediately impacts the inter-core communication performance and thereby the value-cost ratio of such systems. We present the design of a real-time operating system simulator that allows to evaluate the different multicore synchronisation mechanisms of the real-time research community regarding their fitness for automotive hard real-time applications. You can reuse the key design idea of this simulator for any simulation based tool for the early timing evaluation of different real-time mechanisms, e. g. scheduling algorithms.

SimTrOS: A heterogenous abstraction level simulator for multicore synchronization in real-time systems

Abstract To provide a common ground for the comparison of real-time multicore synchronization protocols we developed a framework that supports heterogenous levels of abstraction for simulated functionality and simulated timing. Our intention is to make the simulator available to the real-time research community and industrial users. For the latter we initially focus on automotive real-time systems. This paper describes the simulation framework and the novel idea of heterogenous abstraction levels that lies at the heart of its design. Notwithstanding the clear focus, we believe that the simulator itself as well as the concept of heterogenous abstraction levels can be useful in a significantly broader way.

Automated planning of charge processes for privately owned electric vehicles

Following the vision of decentrally generated and locally out-balanced renewable electric energy the research project econnect Germany investigates the end user acceptance of Vehicle2Grid and Grid2Vehicle applications. The algorithm used to compute the charging/discharging of individual batteries in electric vehicles (EV) will be an essential factor for end user acceptance. This is because it controls the achievable driving range and the cost savings for the individual user of an electric vehicle. Additionally, the algorithm has to allow for an effective control by the energy provider to compensate for the natural fluctuations of wind and solar energy in the region. As the final authority to decide about charging/discharging needs to be the battery management system of the EV, it is a natural choice to embed the algorithm in an electronic control unit of the car. This paper presents an algorithm designed to meet these requirements and demonstrates that it scales down to the low computing power of embedded automotive systems.