Jose Avelino Delgado

Comparison of fabrication methods for bonded wafer SOI

Summary form only given. The reduction of collector series resistance in bipolar devices and the prevention of back-gate effects in MOS devices is commonly realized through the use of highly doped buried layers and retrograde implanted wells, respectively. For device applications requiring a thick SOI layer (approximately 10 mu m), this can be achieved by using back-side processing in a wafer-bounding technique. While bipolar devices have been successfully fabricated using this method, the resulting back-side nonuniformities can reduce bounding yield. This shows up as microdebonding after the trench etch used for lateral isolation. Other drawbacks to back-side bonding are difficult front-to-back alignment and a relatively large variation in layer thickness (+1.5 mu m across a 4-in. slice) due to the grind/polish step used for planarization. An improved method of manufacturing thick bonded SOI material using an epitaxial layer on a thin bonded substrate eliminates many of the drawbacks to the back-side bonding approach. This epi-on-bonded method results in an all-frontside material process suitable for use in a complementary bipolar or BICMOS technology.<<ETX>>

UHF2: a 0.6-μm 25-GHz BiCMOS technology for mixed-signal wireless communications applications

A 0.6 micrometers RF BiCMOS technology was developed by the modular integration of a 25 GHz fT, 35 GHz fMAX NPN transistor and high-quality passive components into an existing 0.6 micrometers analog CMOS process. The resultant process technology supports low-cost, mixed-signal RF applications up to 2.5 GHz.

An evaluation of SOI technologies for high performance analog bipolar circuits

Summary form only given. Characterization results of analog circuits fabricated on dielectric isolation (DI), bonded wafer SOI and multiple implant separation by implantation of oxygen (SIMOX) substrates are reported. The DI parts were manufactured using standard processing technology while the SIMOX and bonded wafer SOI circuits utilized the front-side fabrication method. The SIMOX substrates were prepared using three 5E17 implants at an energy of 200 keV and a temperature of 600 degrees C. The anneals were performed at 1285 degrees C for 2 hours. DC parameters for JFET input op amps fabricated on DI, bonded, and SIMOX substrates are presented. Good agreement is seen between the DC parameters for all three materials. However, the input offset voltage was generally higher for bonded and SIMOX substrates. This has been attributed to trench-related defects, based on Wright etched samples and comparisons of single transistors in each technology.<<ETX>>