Jose de Jesus Pineda De Gyvez

Defect-oriented testing for nano-metric CMOS VLSI circuits

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts. The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique

Embedded SRAM bit count is constantly growing limiting yield in systems-on-chip (SoCs). As technology scales into deep sub-100-nm feature sizes, the increased defect density and process spreads make stability of embedded SRAMs a major concern. This paper introduces a digitally programmable detection technique, which enables detection of SRAM cells with compromised stability [with data retention faults (DRFs) being a subset]. The technique utilizes a set of cells to modify the bitline voltage, which is applied to a cell under test (CUT). The bitline voltage is digitally programmable and can be varied in wide range, modifying the pass/fail threshold of the technique. Programmability of the detection threshold allows tracking process variations and maintaining the optimal tradeoff between test quality and test yield. The measurement results of a test chip presented in the paper demonstrate the effectiveness of the proposed technique

Yield modeling and BEOL fundamentals

The advent of deep submicron technologies with larger die sizes lends itself to an increase in fabrication cost. An appropriate yield forecast renders significant benefits in both time-to-market and manufacturing cost prediction. Yield forecasting is essential for the development of new products as it effectively shows if a design is feasible of meeting its cost objectives or not. In mature manufacturing processes, spot defects are the main detractors in the successful outcome of an IC. Their manifestation is as local disturbances of silicon layer structures. Spot defects are in essence random phenomena occurring on the wafer with certain stochastic size, spatial distribution, and frequency of occurrence per unit area. To verify the robustness of an IC it is necessary to extract its “critical areas”. The so-called critical areas are the places in the layout where defects can induce and IC faulty behavior such as a short or a break circuit. A figure of merit that measures the layouts robustness is obtained as the ratio of the total critical area to the layout area. This figure of merit is known as defect sensitivity. Knowledge of the designs defect sensitivity and the stochastic behavior of defects in the manufacturing line is used to ultimately predict yield. This tutorial reviews the basics on spot defect modeling, critical area modeling and its application in interconnect yield analysis.

Pre-layout prediction of interconnect manufacturability

Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires, and cuts, which result in broken wires. The probability of failure is therefore determined by the geometry of the routing channels and the distribution of defect sizes. Since the wire spacing and width are usually fixed, and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts, and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Since the probability of failure is determined by the behavior of the wires averaged over the entire interconnect, the application of System Level Interconnect Prediction (SLIP) techniques is particularly appropriate. This paper presents a method for utilizing previously developed techniques for wire length estimation and layer assignment and applies them to the problem of cut and bridge functional yield estimation.

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.

Ultra-low-power digital design with body biasing for low area and performance-efficient operation

We present a design methodology towards minimum-area maximum-performance designs in sub-/ near-threshold operation. Our methodology is based on a new metric called performance-per-area. Unlike conventional gate sizing, we use forward body biasing at synthesis time to render faster, smaller and more energy-efficient circuits. Our theory introduces body biasing into delay and energy models in the form of nonlinear derating functions that can easily be fitted to a technology node. The methodology is validated using an industrial microprocessor consisting of approximately 31 K gates and 3.7 K flip-flops in CMOS 90 nm. We obtain 4.2x better EDP, 3.8x higher speed and 9% smaller area than the non-body-biased counterpart.

Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits

A new approach for analog fault modeling and simulation is presented. The proposed approach utilizes the sensitivity of the circuit’s DC node voltages to the process variations and consequently the current deviance so as to differentiate the faulty behavior. A systematic method is proposed for the fault discrimination to minimize the probability that the circuit is accepted as a fault-free when it is faulty. Tests are generated and evaluated taking into account the potential fault masking effects of process spread on the faulty circuit responses. The introduced fault model is validated on a time-interleaved sample-and-hold circuit. Simulation results demonstrate the effectiveness of the model.

Multi-VDD Testing for Analog Circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.

Threshold Voltage Mismatch (\DeltaVT) Fault Modeling

A reduced intrinsic threshold voltage (V/sub T/) in addition to its variability has a direct impact on circuit design. Worst-case design styles assume that all transistors use the same worst-case V/sub T/ whose average and standard deviation come from inter-die statistical variations. However, intra-die differences, such as random local V/sub T/ variations are not considered and may pose a serious problem for designs based on low-voltage low-power premises, e.g. clock skews, excessive leakage current, out of spec critical-path delays, etc. This paper formulates a fault model based on threshold voltage mismatch and analyzes its impact on circuit design. Simulation and experimental results support the fault model.

Low energy FPGA interconnect design

FPGAs are not energy efficient largely due to their programmable, capacitively loaded interconnect. We propose a new low energy FPGA interconnect architecture that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study, based on circuit simulations using SPICE in CMOS 0.13 micron process technology, illustrates that a 41% energy reduction can be achieved compared to the conventional techniques. A one to one comparison between NMOS based switches and the proposed DTMOS based switches reveal that the latter have a 36% lower power-delay product. We also show through a model analysis and circuit simulations that using low swing on interconnect, a timing budget can be met at 30% less energy consumption.