Jose Fridman

The TigerSHARC DSP architecture

This highly parallel DSP architecture based on a short-vector memory system incorporates techniques found in general-purpose computing. It promises sustained performance close to its peak computational rates of 900 MFLOPS (32-bit floating-point) or 3.6 BOPS (16-bit fixed-point).

Discrete wavelet transform: data dependence analysis and synthesis of distributed memory and control array architectures

We perform a thorough data dependence and localization analysis for the discrete wavelet transform algorithm and then use it to synthesize distributed memory and control architectures for its parallel computation. The discrete wavelet transform (DWT) is characterized by a nonuniform data dependence structure owing to the decimation operation it is neither a uniform recurrence equation (URE) nor an affine recurrence equation (ARE) and consequently cannot be transformed directly using linear space-time mapping methods into efficient array architectures. Our approach is to apply first appropriate nonlinear transformations operating on the algorithms index space, leading to a new DWT formulation on which application of linear space-time mapping can become effective. The first transformation of the algorithm achieves regularization of interoctave dependencies but alone does not lead to efficient array solutions after the mapping due to limitations associated with transforming the three-dimensional (3-D) algorithm onto one-dimensional (1-D) arrays, which is also known as multiprojection. The second transformation is introduced to remove the need for multiprojection by formulating the regularized DWT algorithm in a two-dimensional (2-D) index space. Using this DWT formulation, we have synthesized two VLSI-amenable linear arrays of LPEs computing a 6-octave DWT decomposition with latencies of M and 2M-1, respectively, where L is the wavelet filter length, and M is the number of samples in the data sequence. The arrays are modular, regular, use simple control, and can be easily extended to larger L and J. The latency of both arrays is independent of the highest octave J, and the efficiency is nearly 100% for any M with one design achieving the lowest possible latency of M.

Data alignment for sub-word parallelism in DSP

Data alignment and code size expansion are two problems of sub-word parallel (SWP) computation. In this paper we propose a new solution to data alignment in a recently introduced SWP-extended digital signal processor, and present details of an application example. This data alignment technique offers a reduction in overhead compared to other solutions in the literature, in that it does not require aggressive loop unrolling and can be tightly scheduled in software.

Performance analysis of turbo decoder for 3GPP standard using the sliding window algorithm

We analyze the performance of a fixed-point turbo decoder using two sliding window algorithms for the 3GPP standard. We show that the bit and frame error rate performance of the sliding window scheme strongly depends on the guard window size. Simulation results also indicate that small guard window sizes can significantly decrease the iteration gain for large frames.

A 333-MHz dual-MAC DSP architecture for next-generation wireless applications

We introduce the first DSP core developed at the Analog Devices and Intel Joint DSP Development Center. The 16-bit fixed-point core combines some of the best features of traditional DSPs and micro-controllers and compares favorably with dual-MAC DSPs on DSP specific benchmarks and with micro-controllers on micro-controller specific benchmarks. In addition, the core supports a rich set of alignment independent packed byte instructions to enable an efficient implementation of 3G algorithms in next-generation wireless applications. The deep and fully interlocked pipeline allows the core to run at 333-MHz in the 0.18-/spl mu/m TSMC process.

Performance Analysis of Sliding Window Turbo Decoding Algorithms for 3GPP FDD Mode

In this paper we analyze the performance of a turbo decoder using two sliding window algorithms for the frequency division duplex (FDD) mode of the Third Generation Partnership Project (3GPP) standard. Focusing on the solution for the user equipment, we compare fixed-point realizations of the sliding window algorithms in terms of the computational complexity and memory requirements. We show that the bit and frame error rate performance of the sliding window scheme strongly depends on the guard window size. Furthermore, simulation results indicate that relatively small guard window sizes can significantly decrease the iteration gain for large frames. Finally, optimization of the windowing parameters achieves the desired trade-off between the performance degradation introduced by a windowing approach and the computational complexity and memory utilization.

A new parallel DSP with short-vector memory architecture

This paper presents a new highly-parallel DSP architecture based on a short-vector memory system developed at Analog Devices, Inc. This DSP incorporates for the first time in an embedded processor a number of techniques found in general purpose computing, such as branch prediction, deep and fully interlocked pipeline, and SIMD instruction execution. By means of its short-vector high-bandwidth memory system it is able to deliver sustained performance that is close to its peak computational rates of 1.5 GFLOPS (32-bit floating-point), or 6 GOPS (16-bit fixed-point).

Cached memory performance characterization of a wireless digital baseband processor

We present performance analysis results of the MSP500 digital baseband (DBB) platform, a system developed at Analog Devices Inc., targeted at cellular handsets supporting the GSM, GPRS, and EDGE communication standards. We focus on a particular member of the MSP500 family, the AD6532 device, which integrates a Blackfin/spl reg/ core, and examine the execution time performance of a number of wireless physical layer software components from the perspective of an instruction- and data-cached memory hierarchy. The Blackfin is a 16-bit fixed-point core that combines some of the best features of DSPs and micro-controllers, and has support for a cached memory system.

Distributed Memory Parallel Architecture Based on Modular Linear Arrays for 2-D Separable Transforms Computation

A framework for mapping systematically 2-dimensional (2-D) separable transforms into a parallel architecture consisting of fully pipelined linear array stages is presented. The resulting model architecture is characterized by its generality, high degree of modularity, high throughput, and the exclusive use of distributed memory and control. There is no central shared memory block to facilitate the transposition of intermediate results, as it is commonly the case in row-column image processing architectures. Avoiding shared central memory has positive implications for speed, area, power dissipation and scalability of the architecture. The architecture presented here may be used to realize any separable 2-D transform by only changing the coefficients stored in the processing elements. Pipelined linear arrays for computing the 2-D Discrete Fourier Transform and 2-D separable convolution are presented as examples and their performance is evaluated.