Jose Luis Garcia-Gervacio

A design methodology for logic paths tolerant to local intra-die variations

Process variations have become a critical issue influencing the performance of nanometer digital circuits at gigascale integration; variations are classified in two types: inter-die and intra-die. Whereas inter-die variations affect the deviation of performance distribution in a lot of chips, intra-die variations affect the media of performance distribution. The present work proposes a new design methodology for designing logic paths tolerant to local intra-die variations. A library of transistor structures with different degree of delay variability is defined. Transistors from the logic gates are replaced with these structures according to selection criteria to improve the delay tolerance to process variation on logic paths. Delay variability is reduced at the expense of circuit area. Results show a significant variability reduction for a moderate increment of area and power consumption.

Small-delay defects detection under process variation using Inter-Path Correlation

Detection of Small Delay Defects (SDDs) is a major concern in modern circuits using nanometer technologies. They are difficult to test and an important source of test escapes, and even when SDDs do not produce functional failures, they represent a reliability risk. The detection of these defects aggravates in the presence of process variations. In this paper, a methodology to detect SDDs in the presence of process variations using delay correlation information between paths of a circuit is proposed. This methodology exploits the concept that for two highly correlated paths, an important part of the delay variance in one path can be described by the delay variance in the second path. The methodology has been further extended to consider multiple path correlation thus improving the detection of SDDs. This methodology is able to distinguish delay defects from process variations. A metric is also proposed to quantify the SDD screenable variance that represents the percentage of variance where a defect can be detected. A statistical timing analysis framework has been developed and implemented to compute timing information and Inter-Path Correlation (IPC). Spatial and structural correlation, and random dopant fluctuations are considered. Simulation results in 74LS85 and ISCAS85 benchmark circuits evince the feasibility of the proposed methodology.

Computing the Detection Probability for Small Delay Defects of Nanometer ICs

Interconnect imperfections have become an important issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Those SDDs not detected during testing may pose a reliability problem. Furthermore, nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a methodology to compute the Detection Probability (DP) of resistive open and bridge defects using a statistical timing framework that takes into account process variations and other nanometer issues is proposed. The DP gives the sensitivity of the circuit performance to a given resistance range of the defect. The efficiency issue when analyzing large circuits is alleviated using stratified sampling techniques to reduce the space of possible analyzed defect locations This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable DP in order to improve the test quality.

Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs

Interconnect imperfections have become an issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Furthermore, those SDDs not detected during testing may pose a reliability problem. Nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a technique to compute the probability of detection of resistive opens causing SDDs considering process variations is proposed. This technique is used to estimate the Statistical Fault Coverage (SFC) of a circuit. In order to estimate the SFC of a circuit, the delays are propagated using statistical timing analysis, and the analyzed space of possible delay fault locations is obtained using stratified sampling techniques. This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable fault coverage in order to improve their test quality.

SCADA system design: A proposal for optimizing a production line

By addressing a series of authorization requirements for a production line, this research paper deals with the implementation of a SCADA system that provides information of the production line status in real time, which help in the decision-making during and after the process. The cost and difficulty of use, installation and maintenance are some of the common problems in the SCADA systems, the proposed solution considers these problems by providing a low cost platform and easy to operate with the possibility to implement a basic system with a microcontroller card or the integration of subsystems with high-end devices, integrating various hardware technologies, adding flexibility and scalability to system features. The solution includes a web app, a data warehouse, as well as real time communication techniques between the different levels. It is proposed to use WebSocket technology as a means of communication between slaves and masters levels. Another important feature of the proposal is to manage the logistics in a master server to coordinate each node of the process, which can be reconfigurable and controlled automatically with specified parameters or manually. The system counts with a monitoring option and a remote control for the production line, making information accessible from anywhere and on any device.

Direct application of Padé approximant for solving nonlinear differential equations

This work presents a direct procedure to apply Padé method to find approximate solutions for nonlinear differential equations. Moreover, we present some cases study showing the strength of the method to generate highly accurate rational approximate solutions compared to other semi-analytical methods. The type of tested nonlinear equations are: a highly nonlinear boundary value problem, a differential-algebraic oscillator problem, and an asymptotic problem. The high accurate handy approximations obtained by the direct application of Padé method shows the high potential if the proposed scheme to approximate a wide variety of problems. What is more, the direct application of the Padé approximant aids to avoid the previous application of an approximative method like Taylor series method, homotopy perturbation method, Adomian Decomposition method, homotopy analysis method, variational iteration method, among others, as tools to obtain a power series solutions to post-treat with the Padé approximant.AMS Subject Classification34L30

Detectability analysis of small delays due to resistive opens considering process variations

Resistive opens in vias and interconnection lines have become an issue in modern nanometer technologies. These defects may produce small delays which are difficult to detect and may pose a reliability problem. In this paper, a statistical timing analysis framework is used to analyze the detectability of small delays due to resistive opens considering process variations. A statistical methodology to estimate the fault coverage of these defects is proposed. Using the proposed methodology, the statistical fault coverage of resistive opens producing small delays is evaluated for some ISCAS benchmark circuits.

Low VDD and body bias conditions for testing bridge defects in the presence of process variations

Bridge defects are an important manufacturing defect that may escape test causing reliability issues. It has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods lowering test quality. Therefore, advances in test methodologies to enhance bridge detection are required. In this work a Statistical Timing Analysis Framework (STAF) is used to compute the probability of detection of bridge defects for different VDD and RBB values. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage (SFC). The STAF allows to capture properly the behavior of the mean and a standard circuit delay when VDD and RBB change. Furthermore, the STAF uses a realistic bridge defect model suitable to consider appropriately the impact of VDD and RBB on delay increase. This methodology is applied to some ISCAS benchmark circuits implemented in a commercial 65nm CMOS technology. The obtained results of several ISCAS benchmark circuits show clearly that the Statistical Fault Coverage (SFC) increases significantly when VDD is lowered, and increases even more when RBB is applied at Low VDD. The test conditions to improve resistive bridge detection combining Low VDD and Reverse Body Bias (RBB) under a delay based test are determined. It is shown that the impact of RBB on bridge detection improves significantly for a sufficient low value of VDD. The values of Low VDD and RBB can be selected considering the tradeoff between fault coverage and test time penalization.

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias

Bridge defects are an important manufacturing defect that may escape test. Even more, it has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods. Therefore, advances in test methodologies to deal with nanometer issues are required. In this work the feasibility of using Low VDD and body bias in a delay based test to detect resistive bridge defects in CMOS nanometer circuits is analyzed. The detection of bridge defects using a delay based test in nanometer circuits is strongly influenced by: (1) spatial correlation of the process parameters such as length, width and oxide thickness of the transistor, (2) random placement of dopants, and (3) the signal correlation due to reconvergent paths. Because of this, in this work a Statistical Timing Analysis Framework (STAF) is used to analyze the possibilities of detection of bridge defect using a delay based test. The STAF considers different values of VDD and body bias. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage that gives a more realistic measure of the degree of detection of the defect. This methodology is applied to some ISCAS benchmark circuits implemented in a 65nm CMOS technology. The obtained results show the feasibility of the proposed methodology.

TCAD analysis and modeling for NBTI mechanism in FinFET transistors

Aging is an important concern in long term reliability of semiconductor devices. In this regard, Bias Temperature Instability (BTI) is considered the major aging mechanism in nanometer regime, particularly in FinFET devices. Therefore, a well understanding of BTI mechanism in FinFET technology is of high interest. In this paper, a three-dimensional TCAD analysis about the impact of negative BTI (NBTI) FinFET technology is presented. In addition, a new NBTI degradation model is proposed for FinFET devices that can be incorporated in Spice which allow to consider aging of a circuit in a design phase. The three-dimensional TCAD analysis is performed using Synopsys Sentaurus tool. Results from the proposed model agree with Sentaurus degradation results.