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Dive into the research topics where José Marín is active.

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Featured researches published by José Marín.


SIAM Journal on Scientific Computing | 2003

Preconditioning Sparse Nonsymmetric Linear Systems with the Sherman--Morrison Formula

Rafael Bru; Juana Cerdán; José Marín; José Mas

Let Ax=b be a large, sparse, nonsymmetric system of linear equations. A new sparse approximate inverse preconditioning technique for such a class of systems is proposed. We show how the matrix A0-1 - A-1, where A0 is a nonsingular matrix whose inverse is known or easy to compute, can be factorized in the form


Annals of Nuclear Energy | 1998

High order backward discretization of the neutron diffusion equation

D. Ginestar; G. Verdú; Vicente Vidal; Rafael Bru; José Marín; J.L. Muñoz-Cobo

U\Omega V^T


SIAM Journal on Matrix Analysis and Applications | 2010

Improved Balanced Incomplete Factorization

Rafael Bru; José Marín; José Mas; Miroslav Tu ring; ma

using the Sherman--Morrison formula. When this factorization process is done incompletely, an approximate factorization may be obtained and used as a preconditioner for Krylov iterative methods. For A0=sIn, where In is the identity matrix and s is a positive scalar, the existence of the preconditioner for M-matrices is proved. In addition, some numerical experiments obtained for a representative set of matrices are presented. Results show that our approach is comparable with other existing approximate inverse techniques.


IEEE Transactions on Computers | 2009

A Complexity-Effective Out-of-Order Retirement Microarchitecture

Salvador Vicente Petit Martí; Julio Sahuquillo Borrás; Pedro Juan López Rodríguez; Rafael Ubal Tena; José Marín

Abstract Fast codes capable of dealing with three-dimensional geometries, are needed to be able to simulate spatially complicated transients in a nuclear reactor. We propose a new discretization technique for the time integration of the neutron diffusion equation, based on the backward difference formulas for systems of stiff ordinary differential equations. This method needs to solve a system of linear equations for each integration step, and for this purpose, we have developed an iterative block algorithm combined with a variational acceleration technique. We tested the algorithm with two benchmark problems, and compared the results with those provided by other codes, concluding that the performance and overall agreement are very good.


SIAM Journal on Scientific Computing | 2014

Preconditioned Iterative Methods for Solving Linear Least Squares Problems

Rafael Bru; José Marín; José Mas; Miroslav Tůma

In this paper we improve the BIF algorithm which computes simultaneously the LU factors (direct factors) of a given matrix and their inverses (inverse factors). This algorithm was introduced in [R. Bru, J. Marin, J. Mas, and M. Turma, SIAM J. Sci. Comput., 30 (2008), pp. 2302-2318]. The improvements are based on a deeper understanding of the inverse Sherman-Morrison (ISM) decomposition, and they provide a new insight into the BIF decomposition. In particular, it is shown that a slight algorithmic reformulation of the basic algorithm implies that the direct and inverse factors numerically influence each other even without any dropping for incompleteness. Algorithmically, the nonsymmetric version of the improved BIF algorithm is formulated. Numerical experiments show very high robustness of the incomplete implementation of the algorithm used for preconditioning nonsymmetric linear systems.


IEEE Transactions on Parallel and Distributed Systems | 2009

FT²EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals

Crispín Gómez Requena; María Engracia Gómez Requena; Pedro Juan López Rodríguez; José Marín

Current superscalar processors commit instructions in program order by using a reorder buffer (ROB). The ROB provides support for speculation, precise exceptions, and register reclamation. However, committing instructions in program order may lead to significant performance degradation if a long latency operation blocks the ROB head. Several proposals have been published to deal with this problem. Most of them retire instructions speculatively. However, as speculation may fail, checkpoints are required in order to rollback the processor to a precise state, which requires both extra hardware to manage checkpoints and the enlargement of other major processor structures, which, in turn, might impact the processor cycle. This paper focuses on out-of-order commit in a nonspeculative way, thus, avoiding checkpointing. To this end, we replace the ROB with a validation buffer (VB) structure. This structure keeps dispatched instructions until they are nonspeculative or mispeculated, which allows an early retirement. By doing so, the performance bottleneck is largely alleviated. An aggressive register reclamation mechanism targeted to this microarchitecture is also devised. As experimental results show, the VB structure is much more efficient than a typical ROB since, with only 32 entries, it achieves a performance close to an in-order commit microprocessor using a 256-entry ROB.Current superscalar processors commit instructions in program order by using a reorder buffer (ROB). The ROB provides support for speculation, precise exceptions, and register reclamation. However, committing instructions in program order may lead to significant performance degradation if a long latency operation blocks the ROB head. Several proposals have been published to deal with this problem. Most of them retire instructions speculatively. However, as speculation may fail, checkpoints are required in order to rollback the processor to a precise state, which requires both extra hardware to manage checkpoints and the enlargement of other major processor structures, which in turn might impact the processor cycle. This paper focuses on out-of-order commit in a nonspeculative way, thus avoiding checkpointing. To this end, we replace the ROB with a validation buffer (VB) structure. This structure keeps dispatched instructions until they are nonspeculative or mispeculated, which allows an early retirement. By doing so, the performance bottleneck is largely alleviated. An aggressive register reclamation mechanism targeted to this microarchitecture is also devised. As experimental results show, the VB structure is much more efficient than a typical ROB since, with only 32 entries, it achieves a performance close to an in-order commit microprocessor using a 256-entry ROB. Index Terms —Instruction level parallelism, out-of-order commit, long latency operations, control dependencies, exception handling.


Computers & Mathematics With Applications | 2002

Iterative schemes for the neutron diffusion equation

Rafael Bru; D. Genstar; José Marín; G. Verdú; José Mas; Thomas A. Manteuffel

New preconditioning strategies for solving


Applied Mathematical Modelling | 2001

Multilevel methods to solve the neutron diffusion equation

D. Ginestar; José Marín; G. Verdú

m \times n


parallel computing | 1999

Parallel m -step preconditioners for the conjugate gradient method

Cristina Corral; Isabel Giménez; José Marín; José Mas

overdetermined large and sparse linear least squares problems using the conjugate gradient for least squares (CGLS) method are described. First, direct preconditioning of the normal equations by the balanced incomplete factorization (BIF) for symmetric and positive definite matrices is studied, and a new breakdown-free strategy is proposed. Preconditioning based on the incomplete LU factors of an


Numerical Algorithms | 2017

Low-rank updates of balanced incomplete factorization preconditioners

Juana Cerdán; José Marín; José Mas

n \times n

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José Mas

Polytechnic University of Valencia

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Juana Cerdán

Polytechnic University of Valencia

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Rafael Bru

Polytechnic University of Valencia

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Pedro Juan López Rodríguez

Polytechnic University of Valencia

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Crispín Gómez Requena

Polytechnic University of Valencia

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G. Verdú

Polytechnic University of Valencia

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D. Ginestar

Polytechnic University of Valencia

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Cristina Corral

Polytechnic University of Valencia

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D. Genstar

Polytechnic University of Valencia

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