Jose Moreira

Implementation of an economic jitter compliance test for a multi-gigabit device on ATE

State of the art communication devices combine multiple high-speed interfaces like SFI4.2 and XAUI with speeds up to 3.2 gigabits per second (Gbps) on a single CMOS chip. One key parameter common to the specification of these interfaces is the jitter observed on the transmitters. Existing automated test approaches are not able to cover this parameter during production test at a reasonable economical performance, determined by the following items: capital investment, time-to-market (TTM) and test cost per chip. This work includes a discussion of the need for jitter separation, a thorough review of jitter separation algorithms and also presents the results of a specific jitter separation approach with an at-speed ATE system.

Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment

State-of-the-art automated test equipment is now able to address I/O data rates in the 10 Gigabits-per-second (Gbps) data range. This is an achievement that remained the domain of racks of bench instrumentation and appeared very challenging for ATE systems until just a few years ago. With the I/O data rates of CMOS integrated circuits continuing to grow, the challenges for designing automated test equipment continue to increase. This paper provides a discussion of the signal integrity challenges that automated test equipment must surpass to successfully characterize future I/O interfaces that could even reach 40 Gbps.

Addressing the Broadband Crosstalk Challenges of Pogo Pin Type Interfaces for High-Density High-Speed Digital Applications

Input-output (I/O) cells in integrated circuit devices (ICs) are pushing data-rates to speeds of 5 Gb/s and above with an ever increasing number of pins. This is creating significant challenges for the automated test equipment (ATE) industry to develop appropriate interfaces that provide the needed performance. This article discusses crosstalk issues in high density, high performance ATE interconnects which usually include pogo pin type interfaces, mixed-dielectric printed circuit board (PCB) stack-ups with long differential traces, and innovative pogo/PCB via geometries. To demonstrate the crosstalk challenge and how to address it, a pogo pin assembly and pogo via design is analyzed as an example. This practical approach addresses aspects of creating the high performance interconnect such as pogo and PCB design issues, EM modeling, and measurements.

Development of a pogo pin assembly and via design for multi-gigabit interfaces on automated test equipment

I/O cells operating up to 10 Gb/s, are now becoming standard blocks in complex integrated circuits (ICs). Integration of these multiple I/O cells in conjunction with other cores (e.g. mixed-signal) and higher power requirements has increased the pin count for some devices to above one thousand pins. This presents tough challenges for the automated test equipment (ATE) industry, in terms of developing solutions to address the data rate and routing density. This paper demonstrates a novel approach for designing a high density Pogo pin transition to a multilayer planar PCB structure that achieves not only the required 10 Gb/s performance but also maintains the necessary density, and cost requirements that are inherent to an ATE solution.

Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications

Relays are some of the most frequently used components on test fixtures for automated test applications. With data-rates of current I/O interfaces already reaching 5 Gbps and beyond in desktop applications and expected to continue to increase, test engineers must make the decision to continue using relays on the high-speed signal lines, or remove the relays from the test fixture signal paths and sacrifice the flexibility they provide. This paper presents some results and guidelines on using relays in test fixtures for 10 Gbps applications. A commercially available relay was selected and integrated into a typical ATE test fixture design. Special consideration was given to the footprint optimization through 3D-EM simulation and the use of passive equalization to compensate for some of the relay losses. The paper concludes with measurements of an experimental test fixture using an ATE system running 10 Gbps.

Driver sharing challenges for DDR4 high-volume testing with ATE

The need for larger and faster memories has been a constant requirement in the last decades together with keeping memory costs constant or lower. This presents a significant challenge for cost effective memory testing, not only because of the increased data rates but also the pressure to keep memory testing costs down. This paper addresses one of these challenges, which is the development of driver-sharing designs to allow the development of DDR test solutions with a high number of sites. This paper will describe in detail the challenges that high-volume ATE testing of DDR4 presents in regard to driver sharing, allowing the test engineer to better grasp the problems associated with DDR4 high-volume ATE testing.

An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System

This paper presents an active test fixture approach for at-speed functional testing of high-speed I/O interfaces with automated test equipment that is able to reach data rates of 40 Gbps and above. At these data rates signal integrity is critical. Because of this we will not only discuss the solution in terms of its instrumentation but also the challenges of getting the signal to the DUT with the needed parametric performance. We will also show some results with a real application running at 40 Gbps.

Design of a High Bandwidth Interposer for Performance Evaluation of ATE Test Fixtures at the DUT Socket

When using automatic test equipment (ATE) or a bench instrumentation measurement setup for measuring integrated circuits for high-speed digital applications it is critical to understand the performance obtained at the connection point between the DUT package and the measurement system, which usually is the DUT socket. In this paper we will explain how to design an interposer with performance above 20 GHz that can be used to probe or stimulate signals at the DUT socket. With this capability it is then possible not only to measure the performance at the DUT socket but also to use the measured data for focus calibration of the measurement system allowing higher measurement accuracy.

An Active Test Fixture Approach for Testing 28 Gbps Applications Using a Lower Data Rate ATE System

With some applications already requiring data rates above 12.8 Gbps (e.g. 28 Gbps) and given the fact that the current fastest ATE pin electronics card available in the market can only reach 12.8 Gbps, there is a challenge to provide an ATE based solution for these data rates. Since the market for these applications has not justified until now the development of a 28 Gbps ATE pin electronics card, we propose in this paper an active test fixture approach to test application requiring data rates in the 12.8 Gbps to 40 Gbps range using available pin electronics channels with a maximum data rate of 12.8 Gbps together with SiGe MUX and DEMUX modules, frequency multipliers, frequency dividers, band pass filters and amplifiers. This solution does not require any external instrumentation or any modification of the ATE system. We will present results at 28 Gbps using a proof of concept prototype in a loop back configuration. We will also discuss how to address the test fixture design challenges at these data rates.

Development of an ATE test cell for at-speed characterization and production testing

This paper describes the development of a test cell intended for thorough characterization and production testing of a complex multigigabit IC. The objective of this project was to provide a straightforward way to transition from characterization testing to the early production ramp with minimal effort while at the same time not restricting or limiting thorough characterization of the IC. This included providing the flexibility for the Test Engineer being able to use any external measurement instrument required for characterizing the DUT.