Josef Haid

Automated Power Characterization for Run-Time Power Emulation of SoC Designs

With the advent of increasingly complex systems, the use of traditional power estimation approaches is rendered infeasible due to extensive simulation times. Hardware accelerated power emulation techniques, performing power estimation as a by-product of functional emulation, are a promising solution to this problem. However, only little attention has been awarded so far to the problem of devising a generic methodology capable of automatically enabling the power emulation of a given system-under-test. In this paper, we propose an automated power characterization and modeling methodology for high level power emulation. Our methodology automatically extracts relevant model parameters from training set data and generates an according power model. Furthermore, we investigate the automation of the power model hardware implementation and the automated integration into the overall system’s HDL description. For a smart card controller test-system the automatically created power model reduces the average estimation error from 11.78% to 4.71% as compared to a manually optimized one.

An emulation-based real-time power profiling unit for embedded software

The power consumption of battery-powered and energy-scavenging devices has become a major design metric for embedded systems. Increasingly complex software applications as well as rising demands in operating times while having restricted power budgets make power-aware system design indispensable. In this paper we present an emulation-based power profiling approach allowing for real-time power analysis of embedded systems. Power saving potential as well as power-critical events can be identified in much less time compared to power simulations. Hence, the designer can take countermeasures already in early design stages, which enhances development efficiency and decreases time-to-market. Accuracies achieved for a deep submicron smart-card controller are greater than 90% compared to gate-level simulations.

A side channel attack countermeasure using system-on-chip power profile scrambling

Since the discovery that hardware used for cryptographic applications could leak secret information through its power or radiation profile a wide range of possible attack methods has been published. The rapid evolution of these side-channel attacks made it increasingly important to minimize this possible information leakage. Additionally timing information also derived from this power profile is used to control fault-attack campaigns to drive the system into an unintended state. Therefore a wide range of leakage countermeasures has been developed for dedicated cryptographic hardware. Contrariwise only little work is available concerning power profile scrambling techniques for cryptographic software implementations running on general purpose architectures. Such implementations often include power management hardware to cope with several power budget constraints which could be used to influence the systems power consumption during run-time. This paper proposes a novel side channel attack countermeasure technique using such power management methods in combination with techniques for power profile manipulation. State-of-the-art power estimation hardware using a reduced power model allows for the efficient on-line monitoring and manipulation of the power consumption and radiation profile.

A secure hardware module and system concept for local and remote industrial embedded system identification

Smart maintenance constitutes an essential concept in Industry 4.0, where industrial devices report their maintenance status to remote back end systems and thus predictive maintenance can be intelligently scheduled and carried out locally at the affected device. This status data must be securely assignable to the claimed device identities when transmitted remotely. Furthermore, during the actual maintenance task, the service technician must be able to trustworthily identify the correct target device. Unfortunately, current systems typically lack cryptographic authentication and a secure storage for the required credentials, causing identity impersonation as a major threat. In this paper we present a secure NFC-enabled hardware module for industrial embedded systems with a secure identity, enabling local identification by means of the proximity based contact-less technology Near Field Communication (NFC), and remote identification via a contact-based interface, thus helping to prevent device impersonation attacks, device clones and human errors on device identification. A proof of concept utilizing an Infineon security controller capable of elliptic curve cryptography demonstrates the concepts feasibility.

NIZE - a Near Field Communication interface enabling zero energy standby for everyday electronic devices

Standby power consumption of electric devices is a growing waste of energy. Between 5% and 14% of the residential electrical power consumption is caused by devices being in standby mode. Depending on the device type, more than 50% of standby power consumption could be saved by applying state-of-the-art power management techniques. By implementing a zero energy standby design and outsourcing power consuming user interfaces, even more electrical power can be saved. Here we present a novel Near Field Communication (NFC) interfacing method for everyday electronic devices. By implementing this interface, the target device can be shut down during idle times. Thus, standby power consumption is eliminated completely. If user interaction is requested, NFC provides the electrical energy to switch on the target devices power supply and to start the device. Furthermore, any control, status, and maintenance information can be transmitted over NFC. By outsourcing high power dissipating and unoptimized user interfaces (touch screens, WiFi, etc.) to the power optimized NFC reader, further energy savings are possible also during running state. This paper demonstrates the implementation and integration of this novel interfacing technique into common consumer electronics. Two implementation approaches are presented. A simple, energy harvesting-based approach illustrates the basic working principle. The second, more sophisticated approach, enables also authentication, encrypted data transfer, user interface outsourcing, configuration and control tasks, etc. A proof of concept is demonstrated by means of an access control terminal.

Power emulation based DVFS efficiency investigations for embedded systems

Power consumption has become a major design constraint in the embedded systems domain and techniques such as dynamic voltage and frequency scaling (DVFS) have emerged to enhance the systems power and energy efficiency. DVFS-enabling voltage regulators influence the performance, power and energy efficiency of such systems, however, this impact is often neglected or considered late in the design process. In this work, we propose DVFS hardware extensions to a power emulation approach for modeling the voltage regulator behavior, which allows for performance, power and energy efficiency investigations of DVFS-enabled embedded systems. The power emulation approach delivers real-time power information in an early design phase, which allows for the exploration of DVFS efficiency before silicon is available. This offers greater freedom to designers to determine the most apt voltage regulator yielding a system that meets performance, power and energy constraints.

A Flexible and Lightweight ECC-Based Authentication Solution for Resource Constrained Systems

RFID-based and NFC-based applications can be found, apart from others, in security critical application fields, such as payment or access control. For this purpose, Elliptic-Curve Cryptography (ECC) is commonly used hardware integrated in resource constrained applications in order to provide authenticity and data integrity. On the one hand, specialized crypto hardware approaches provide good performance and consume low power. On the other hand, they often lack flexibility, caused, for example, by hardware integrated protocols and cryptographic parameters. Here we present a flexible and lightweight ECC-based authentication solution that takes into account resource constrained systems. This technique permits to shift parts of the computational intense ECC calculations from the resource constrained device to the authentication terminal. By employing a security controller with a small multi-purpose hardware acceleration core, high computation speed is achieved and a maximum level of flexibility is maintained at the same time. We demonstrate the feasible implementation of the proposed technique by means of an Android-based reader / smart card system, which represent a prime example of contemporary power-constrained and performance-constrained embedded systems. An ECC-based authentication can be carried out on average within 25 ms and checked against a back-end server within 66 ms in a secured manner. Thus, a secured and flexible one-way authentication system is given that shows high performance. This solution can be utilized in a wide variety of application fields, such as anti-counterfeiting, where flexibility and low chip prices are essential.

Estimation based power and supply voltage management for future RF-powered multi-core smart cards

RF-powered smart cards are constrained in their operation by their power consumption. Smart card application designers must pay attention to power consumption peaks, high average power consumption and supply voltage drops. If these hazards are not handled properly, the smart cards operational stability is compromised. Here we present a novel multi-core smart card design, which improves the operational stability of nowadays used smart cards. Estimation based techniques are applied to provide cycle accurate power and supply voltage information of the smart card in real time. A supply voltage management unit monitors the provided power and supply voltage information, flattens the smart cards power consumption and prevents supply voltage drops by means of a dynamic voltage and frequency scaling (DVFS) policy. The presented multi-core smart card design is evaluated on a hardware emulation platform to prove its proper functionality. Experimental tests show that harmful power variations can be reduced by up to 75% and predefined supply voltage levels are maintained properly. The presented analysis and management functionalities are integrated at a minimal area overhead of 10.1%.

ESTADO — Enabling smart services for industrial equipment through a secured, transparent and ad-hoc data transmission online

The advent of initiatives like Industry 4.0 promises increased operational efficiency through smart services and interconnected devices. To enable smart maintenance services for todays and future industrial equipment, regular status information must be transmitted from device customers to maintenance service providers over the Internet. However, simply attaching an industrial device to the Internet often leads to a security and privacy nightmare. Transparency about when and what data is being transmitted is of crucial interest to a customer. During transport, data must be protected against modifications and disclosure. A maintainer requires trust in the datas origin and integrity. In this paper, we propose ESTADO, a system that enables smart services by providing the necessary connectivity from industrial equipment to service providers for device state tracking. Our system design focuses on the migration of current devices and the security aspect. Using a non-permanent NFC based connection, connectivity is only established ad-hoc on customer demand, and any data transmission is fully transparent to a customer. We study our design through a prototype implementation using an Infineon security controller and evaluate the security, usability and deployment aspects of our solution.

Emulation-Based Test and Verification of a Design's Functional, Performance, Power, and Supply Voltage Behavior

Test and verification are essential parts during a products development cycle. Simulation and emulation are well known techniques to test and verify the functionality of a design-under-test (DUT) before its tape-out. However, there are additional issues like peak power consumption and supply voltage drops, which can compromise a hardwares functionality. These issues are only partly covered by nowadays functional hardware emulation test and verification approaches. This paper presents a comprehensive emulation methodology. It combines functional hardware emulation with model-based performance, power, and supply voltage analysis techniques. The DUT, which has to be available in a hardware description language, is integrated into a FPGA along with designated analysis units. These analysis units implement models of the DUTs performance, power consumption, and supply voltage behavior. The presented emulation methodology allows a designer to test designs in such a way that the cycle accurate results are taken online, in real-time, and verify both functional and performance behavior, as well as power consumption and supply voltage levels. The proposed comprehensive emulation methodology is used, as an example of application, to verify the design of a LEON3 multi-core processor system as well as a RF-powered contacatless smart card. The depicted results demonstrate that this emulation approach is suitable to detect functional misbehavior caused by power and supply voltage hazards and how they influence the performance of the system.