Josef Lutz

Challenges Regarding Parallel Connection of SiC JFETs

State-of-the-art silicon carbide switches have current ratings that are not sufficiently high to be used in high-power converters. It is, therefore, necessary to connect several switches in parallel in order to reach sufficient current capabilities. An investigation of parallel-connected normally ON silicon carbide JFETs is presented in this paper. The device parameters that play the most important role for the parallel connection are the pinch-off voltage, the gate-source reverse breakdown voltage, the spread in the on-state resistances, and the variations in static transfer characteristics of the devices. Moreover, it is experimentally shown that a fifth factor affecting the parallel connection of the devices is the parasitic inductances of the circuit layout. The temperature dependence of the gate-source reverse breakdown voltages is analyzed for two different designs of silicon carbide JFETs. If the spread in the pinch-off and gate-source reverse breakdown voltages is sufficiently large, there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage. A solution to this problem using individual gate circuits for the JFETs is given. The switching performance of two pairs of parallel-connected devices with different combinations of parameters is compared employing two different gate-driver configurations. Three different circuit layouts are considered and the effect of the parasitic inductances is experimentally investigated. It is found that using a single gate circuit for the two mismatched JFETs may improve the switching performance and therefore the distribution of the switching losses significantly. Based on the measured switching losses, it is also clear that regardless of the design of the gate drivers, the lowest total switching losses for the devices are obtained when they are symmetrically placed.

Power cycling with high temperature swing of discrete components based on different technologies

We present the results of power cycling tests of transfer molded, DCB and copper based power components at temperature swings up to 155 K. The results of the DCB based components are statistically analysed with Weibull distribution. An Analysis of the components after the tests provides an overview on the failure mechanisms. The results of the DCB based, transfer molded components exceed the expectations based on extrapolation of LESIT results.

On the destruction limit of Si power diodes during reverse recovery with dynamic avalanche

The reverse recovery destruction limit of 3.3 kV fast recovery diodes was investigated by measurements and device simulations. Based on a good agreement between the measured destruction limit and current filamentation in simulations, it is proposed that the destruction is triggered by the onset of impact ionization at the n-n/sup +/ junction. The proposed destruction mode has significant similarities with previously described second breakdown at the static breakdown voltage. An approximate analytical model which was derived indicates that avalanche at the n-n/sup +/ junction should become unstable with a time constant on the order of nanoseconds, whereas dynamic avalanche at the p-n junction should be stable. Simulations and measurements show that the reverse recovery safe operating area depends on the n-base width. An approximate equation is proposed to determine the minimum n-base width required for a nondestructive reverse recovery with dynamic avalanche as a function of the reverse peak voltage.

A Novel Diode Structure with Controlled Injection of Backside Holes (CIBH)

In this paper, we present a novel 3.3kV diode structure with controlled injection of backside holes, i.e. CIBH diode. This new diode structure features buried floating p layers at the cathode side. These p doped areas prevent the formation of high electric field strength at the nn+ junction and accordingly avoid the avalanche generation at the nn+ junction. The CIBH diode concept provides, compared to diodes without p layers and the same design, significantly improved dynamic ruggedness and improved soft reverse recovery at low current densities. Simulations and results of the first fabricated diodes show the realizability of this new promising diode concept

Dynamic avalanche and reliability of high voltage diodes

Diode failures are a limiting factor for the reliability of power circuits. One failure reason is dynamic avalanche, Dynamic avalanche can be distinguished in three degrees, and some designs are ru ...

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The effects during reverse recovery of pin power diodes are determined by free carriers and their interaction with the electric field. A density of free carriers higher than the background doping will easily occur in space-charge regions during reverse recovery of high-voltage silicon devices. As a result, a high electric-field strength combined with avalanche generation occurs at the p-n junction. However, if a second region with high electric-field strength arises at the nn+-junction, the situation can become critical. If the second electric-field peak can be suppressed, it is possible to make diodes that are very rugged and show a significantly improved soft-recovery behavior.

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In this paper, we investigate the origin of thermal runaway in the trench power MOSFET of a modern smart power IC technology. Experimental data on the temperature rise during power pulses show that the onset of thermal runaway depends on the biasing condition even if the power pulses have equal power dissipation. The beginning of thermal runaway in this work is denoted by the inflection point in the measured temperature data. For the experimental data points, the onset varies from 340 °C to 520 °C. Comparison of these experimental data with an analysis based on the stability factor shows very good agreement. The stability factor analysis demonstrates that, above the temperature compensation point (TCP), the driving force for thermal runaway is the thermally generated leakage current of the parasitic n-p-n bipolar transistor. The decrease of mobility and, hence, the MOS channel current above the TCP stabilizes the power MOSFET. In contrast, below the TCP, both the increase of the MOS channel current and the parasitic n-p-n bipolar transistor leakage current with temperature contribute to the thermal runaway.

-Junction as the Key to Improved Ruggedness and Soft Recovery of Power Diodes

Standard packaging and interconnection technologies limit the maximal junction temperature (Tjmax) to about 150degC at present. This restriction is caused by the limited power cycling capabilities of Al bond wires and of soft solder joints. Important applications of power devices, however, require operating temperatures of 175degC or even 200degC. To evaluate the suitability of the low temperature joining technique (LTJT) for future module set-up, test samples were prepared and investigated. Already the replacement of only the chip-to-substrate solder joint (one-sided LTJT) improved the power cycling capability at DeltaTj=130K five times or at a DeltaTj=156K ten times compared to the expected capability of soldered and wire bonded devices at these conditions. Application of LTJT to top side chip connections also, i.e. additional replacement of bond wires by silver stripes joined by LTJT (double-sided LTJT), yielded a further increase of power cycling capability

On the Origin of Thermal Runaway in a Trench Power MOSFET

Improvements of power module technologies are investigated in different life time tests. Failure causes like solder fatigue become more important and a limiting factor for lifetime in power cycling tests. Different failure modes of solder joints in relation to power cycling conditions are shown.

Power Cycling at High Temperature Swings of Modules with Low Temperature Joining Technique

Abstract Irradiation techniques are nowadays widely used for carrier lifetime adjustment in silicon power devices because of their very good reproducibility. But still there are missing or incomplete recombination center data for use in device simulation. Based on DLTS and lifetime measurements, the center properties of the most important traps after electron irradiation and annealing with a temperature above 330 °C are determined in this work within a wide temperature range. These parameters have been used for device simulation of irradiated power diodes and correctly explain the temperature dependencies of forward voltage as well as of switching characteristics.