Joseph Straznicky

A hybrid nanomemristor/transistor logic circuit capable of self-programming

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Writing to and reading from a nano-scale crossbar memory based on memristors

We present a design study for a nano-scale crossbar memory system that uses memristors with symmetrical but highly nonlinear current-voltage characteristics as memory elements. The memory is non-volatile since the memristors retain their state when un-powered. In order to address the nano-wires that make up this nano-scale crossbar, we use two coded demultiplexers implemented using mixed-scale crossbars (in which CMOS-wires cross nano-wires and in which the crosspoint junctions have one-time configurable memristors). This memory system does not utilize the kind of devices (diodes or transistors) that are normally used to isolate the memory cell being written to and read from in conventional memories. Instead, special techniques are introduced to perform the writing and the reading operation reliably by taking advantage of the nonlinearity of the type of memristors used. After discussing both writing and reading strategies for our memory system in general, we focus on a 64 x 64 memory array and present simulation results that show the feasibility of these writing and reading procedures. Besides simulating the case where all device parameters assume exactly their nominal value, we also simulate the much more realistic case where the device parameters stray around their nominal value: we observe a degradation in margins, but writing and reading is still feasible. These simulation results are based on a device model for memristors derived from measurements of fabricated devices in nano-scale crossbars using Pt and Ti nano-wires and using oxygen-depleted TiO(2) as the switching material.

A High-Speed Optical Multi-Drop Bus for Computer Interconnections

Buses have historically provided a flexible communications structure in computer systems. However, signal integrity constraints of high-speed electronics have made multi-drop electrical busses infeasible. Instead, we propose an optical data bus for computer interconnections. It has two sets of optical waveguides, one as a fan-out and the other as a fan-in, that are used to interconnect different modules attached to the bus. A master module transmits optical signals which are received by all the slave modules attached to the bus. Each slave module in turn sends data back on the bus to the master module. Arrays of lasers, photodetectors, waveguides, microlenses, beamsplitters and Tx/Rx integrated circuits are used to realize the optical data bus. With 1 mW of laser power, we are able to interconnect 8 different modules at 10 Gb/s per channel. An aggregate bandwidth of over 25 GB/s is achievable with 10 bit wide signaling paths.

Metal-catalysed, bridging nanowires as vapour sensors and concept for their use in a sensor system

Metal-catalysed silicon nanowires were grown between silicon electrodes and exposed to vapours containing HCl or NH3 at reduced pressure. Charge from adsorbed vapour modulated the conductance of the nanowires by changing the number of mobile carriers. Exposing the nanowires to HCl vapour increased the conductance while exposure to NH3 vapour decreased the conductance. The observed results suggest the use of an array of nanowire sensors integrated with silicon electronics. Preliminary area estimates indicate that integrated amplification and signal processing is feasible for an array of 1000 sensors.

Hydrogenated microcrystalline silicon electrodes connected by indium phosphide nanowires

The authors report the connection of two planar hydrogenated silicon (Si:H) electrodes by intersecting and bridging indium phosphide nanowires (InP NWs). A simple metal-semiconductor-metal photoconductor was used as a test vehicle to measure electrical and optical characteristics of the connected InP NWs. This implementation of III-V compound semiconductor nanowires on Si:H combines the characteristics of a direct bandgap semiconductor with the flexible fabrication processes of non-single-crystal silicon platforms that do not require single-crystal substrates.

A High-Speed Optical Multidrop Bus for Computer Interconnections

Signal integrity constraints of high-speed electronics have made multidrop electrical buses infeasible. This high-speed alternative uses hollow metal waveguides and pellicle beam splitters that interconnect modules attached to the bus. With 1 mw of laser power, the bus can interconnect eight modules at 10 gbps per channel and achieves an aggregate bandwidth of more than 25 gbytes per second with 10-bit-wide signaling paths.

Demultiplexers for Nanoelectronics Constructed From Nonlinear Tunneling Resistors

When using linear resistors to implement nanoelectronic resistor-logic demultiplexers, codes can be used to improve the voltage margins of these circuits. However, the resistors which have been fabricated in nanoscale crossbars are observed to be nonlinear in their current versus voltage (I-V) characteristics, showing an exponential dependence of current on voltage; we call these devices tunneling resistors. The introduction of nonlinearity can either improve or degrade the voltage margin of a demultiplexer circuit, depending on the particular code used. Therefore, the criterion for choosing codes must be redefined for demultiplexer circuits built from this type of nonlinear resistor. We show that for well-chosen codes, the nonlinearity of the resistors can be advantageous, producing a better voltage margin than can be achieved with linear resistors

Low cost, injection molded 120 Gbps optical backplane

A low cost, blind mate, injection molded optical backplane is presented. The optical backplane consists of a 12 channel optical broadcast bus operating at 10 Gbps/channel with six blind mate optical output ports spaced 1U apart.

Low Cost, Injection Molded 120 Gbps Optical Backplane

A low cost, blind mate, injection molded optical backplane is presented. The optical backplane consists of a 12 channel optical broadcast bus operating at 10Gbps/channel with six blind mate optical output ports spaced 1U apart.

Fabrication and test of nano crossbar switches/MOSFET hybrid circuits by imprinting lithography

An integrated circuit combining imprinted, nanoscale crossbar switches with metal-oxide field effect transistors (MOSFET) was fabricated and tested. Construction of the circuits began with fabrication of n-channel MOSFET devices on silicon-on-insulator (SOI) substrates using CMOS compatible process techniques. To protect the FET devices as well as provide a flat surface for subsequent nanoimprint lithography, passivation and planarization layers were deposited. Crossbar junctions were then fabricated next to the FETs using imprint lithography to first define arrays of parallel nanowires over which, a switchable material layer was deposited. This was followed by a second imprint proces to construct another set of parallel wires on top of, and orthogonal to the first, to complete the nano-crossbar array with a half pitch (hp) of 50 nm. The switchable crossbar devices were then connected to the gate of the FETs and the resulting integrated circuit was tested using the FET as the output signal follower. This successful fabrication process serves as a proof-of-principle demonstration and a platform for advanced CMOS/nanoscale crossbar hybrid logic circuits.