Jouni Isoaho

A new VLSI-oriented FFT algorithm and implementation

In this paper, we present a new VLSI-oriented fast Fourier transform (FFT) algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. This algorithm can be implemented efficiently using a pipelined architecture. Based on this pipelined architecture, an 8 K FFT ASIC is designed for use in the DVB (Digital Video Broadcasting) application in 0.6 /spl mu/m-3.3 V triple-metal CMOS process.

A Comparison Design of Comb Decimators for Sigma-Delta Analog-to-Digital Converters

This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 μm 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.

A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T

In this paper, we propose a new, reconfigurable algorithm for signal demapping: MUSCOD algorithm, used in DVB-T (Digital Video Broadcasting, Terrestrial version) receivers. The MUSCOD algorithm/architecture supports both hierarchical and nonhierarchical transmission modes. It implements different modulation schemes supported by the standard. We also propose a high-performance, reconfigurable symbol and bit deinterleaver working in conjuction with the demapper. We implement the proposed architecture using 0.6 /spl mu/m 3.3 V CMOS technology. The proposed architecture requires a system clock frequency of 36.57 MHz. It has a maximum throughput of 40.5 Mbits/s and dissipates 0.3 W.

DSP system integration and prototyping with FPGAS

Field Programmable Gate Arrays (FPGAs) offer a cost-effective and flexible technology for DSP ASIC prototype development. In this article, the fast ASIC prototyping concept based on the use of multiple FPGAs is reviewed in different engineering applications. The design experiences of the proposed approach, applied to four different DSP ASIC design projects are presented. The design experiences concerning the selection of the design methodology, application architectures and prototyping technologies are analyzed with respect to efficient system integration and ASIC migration from the FPGA prototype onto first-time functional silicon. Novel prototyping techniques based on using configurable hardware modellers concerning the same objective are studied. Some future goals are outlined to develop an integrated, multipurpose DSP ASIC prototyping environment.

Design of a super-pipelined Viterbi decoder

This paper presents a novel super-pipelined VLSI architecture for Viterbi decoders. This architecture is capable of achieving high throughput in an area-efficient manner and hence it is an attractive architecture for implementing the Viterbi decoder where a large constraint length and high throughput rate are required. The throughput can be linearly increased by increasing the number of basic process elements. The notable advantage is its regularity and flexibility. A Viterbi decode (R=1/2 K=10) is designed in 0.6 /spl mu/m 3.3 V CMOS process to demonstrate the favourable performance of this new architecture.

Design and Implementation of Viterbi Decoder with FPGAs

In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on practical FPGA implementations. Speed performance, easy routability and minimisation of inter-chip communication are used as design criteria. Viterbi decoder, constraint length seven, was designed and simulated with VHDL in Synopsys and Mentor tool environments and further implemented on four Xilinx 4028EX devices using trace-back based architecture. Also partitioning aspects of the decoding algorithm are presented and analysed.

Block-wise extraction of Rent's exponents for an extensible processor

It is envisioned that future system-on-chip hardware platform designs will be based on reuse of a customizable processor core. Consequently, being able to quickly evaluate the key performance metrics associated with specific points in the design space becomes essential. Development of an early design phase performance estimation method for logic blocks of an extensible processor core is described. The processor blocks were systematically synthesized with varying constraints for reference and the corresponding Rents exponents were extracted from the results. The impact of synthesis-originated design space discontinuities on the accuracy of physical performance estimation was evaluated by applying linear regression on the resulting design points.

VHDL macro library testing using BOAR emulation tool

In this paper, the testing of DSP and telecommunication macro library with an FPGA based emulation platform is introduced. The BOAR emulation system is targeted for animating accurately the modern ASIC and processor based systems, which make it also an efficient tool for validating the VHDL based macro components. By utilizing the emulator as a part of an ASIC design process, the testing time of the macros is reduced from several months to a few days, providing also huge savings in ASIC development costs and time.

Strategies for implementation independent DSP system development using HDL based design automation

Digital signal processing applications are suitable for automated library based high-level design, as well as for portable macroblock library based full-custom optimization. Some strategies for benefitting from these properties in technology independent DSP system implementation using VHSIC hardware description language (VHDL) interfaced tools are discussed with some practical examples. Emphasis is placed on the use of the DSP macrocell library.<<ETX>>

DSP ASIC evaluation with fast prototyping

Evaluates the utilization of the fast prototyping concept using the practical design experience gained in DSP ASIC integration on the basis of both schematic capture and VHDL based synthesis. The main emphasis of this work is in the high level problematics: the motivation of prototyping, the selection of prototyping technology, and the design methodology.<<ETX>>