Jovan Djordjevic

A Survey and Evaluation of Simulators Suitable for Teaching Courses in Computer Architecture and Organization

Courses in Computer Architecture and Organization are regularly included in Computer Engineering curricula. These courses are usually organized in such a way that students obtain not only a purely theoretical experience, but also a practical understanding of the topics lectured. This practical work is usually done in a laboratory using simulators of computer systems. Since the open literature contains a variety of simulators being used for such purposes, this paper attempts to give a survey of simulators suitable for teaching courses in computer architecture and organization, to establish the evaluation criteria and to evaluate selected simulators according to these criteria.

Flexible web-based educational system for teaching computer architecture and organization

An important problem in teaching courses in computer architecture and organization is to find a way to help students to make a cognitive leap from the blackboard description of a computer system to its utilization as a programmable device. Computer simulators developed to tackle this problem vary in scope, target architecture, user interface, and support for distance learning. Usually, they include the processor only, lacking the whole-system perspective. The existing simulators mainly focus on the programmers view of the machine and do not provide the designers perspective. This paper presents an educational computer system and its Web-based simulator, designed to help teaching and learning computer architecture and organization courses. The educational computer system is designed to cover a broad spectrum of topics taught in lower division courses. It offers a unique environment that exposes students to both the programmer and the designers perspective of the computer system. The Web-based simulator features an interactive animation of program execution and allows students to navigate through different levels of the educational computer systems hierarchy-starting from the top level with block representation down to the implementation level with standard sequential and combinational logic blocks.

An integrated environment for teaching computer architecture

A major problem in teaching computer architecture and organization courses is how to help students make the cognitive leap that connects their theoretical knowledge with practical experience. Numerous researchers involved in computer architecture and organization education have tackled this problem, resulting in a variety of educational tools for computer system simulation. The tools differ greatly in scope, target architecture complexity, simulation level, and user interface. The available educational systems vary in how they handle digital system simulation. They usually offer tools for creating hardware component libraries, viewing simulation results, and conducting statistical analysis of system performance. Available systems range from sophisticated ones, for complex analysis, to simpler ones that are more readily understood by users, both instructors and students. Beyond system simulation, an educational system should support three key objectives. First, it must cover an extensive range of computer architecture and organization topics. Second, it should graphically depict a computer system, from the block level to the register-transfer level. Third, it must provide the means to follow system functions at the program, instruction, and clock cycle levels.

A hierarchical memory system environment

The paper presents an environment for teaching elements of a computer system memory hierarchy. It is made up of a hierarchical memory system, a reference manual, a software package and a set of laboratory experiments. The hierarchical memory system is devised to cover the virtual memory and translation lookaside buffer, the cache memory, and the main memory. The reference manual provides all implementation details with the appropriate circuits drawings and detailed descriptions. For the devised hierarchical memory system a software package, which includes the graphical simulator with the accompanying tools, is developed. They allow one to carry out the simulation down to the register transfer level by executing a set of laboratory experiments.

CAL2: Computer aided learning in computer architecture laboratory

Computer architecture courses are crucial core courses in computer engineering, electrical engineering, and computer science programs. Dramatic changes in technology, markets, and computer applications create a quite unique and challenging arena for computer architecture instructors and students. The goal is to provide learning environments that will offer hands‐on experience and nurture rapid learning, yet be intuitive and interesting to students. In this paper we discuss the challenges in teaching such courses and present a very flexible educational environment for teaching and learning of computer architecture and organization (CAL2). The CAL2 encompasses a number of software tools that are used both in laboratory settings and at home during self‐study. The CAL2 allows students to write and execute their own assembly language programs, ‘experience’ program execution through graphic simulation and animation, inspect implementation details down to the register transfer level, display timing diagrams, and test their knowledge. In addition, the CAL2 offers a number of features that help instructors define, configure, manage, and administer the laboratory exercises.

CALKAS: a computer architecture learning and knowledge assessment system

The paper presents a Computer Architecture Learning and Knowledge Assessment System named the CALKAS. It is a software tool aimed to be used for teaching Computer architecture and organization. It offers the knowledge assessment and self-learning facilities. The knowledge assessment facilities are meant to be used in laboratory for the lab test and at home for the self-test. The self-learning facilities are meant to be used at home in the process of preparation for the work in the laboratory and for the exam. The CALKAS is developed as a WWW application.

An educational environment for teaching a course in computer architecture and organization

The paper presents an educational environment for teaching a course in Computer architecture and organization. It is made up of an educational computer system, a reference manual, a software package and a set of laboratory experiments. The educational computer system is devised in such a way that it covers the basic structure of a computer system: processor, memory, input/output subsystem and bus. The reference manual provides all implementation details with the appropriate circuits drawings and detailed descriptions. For the devised educational computer system a software package is developed which includes the program development tools and the graphic simulator. They make it possible to develop programs for it and execute them under the graphic simulator. The simulator allows to execute programs at the clock, instruction and program levels and to examine, at any time, the values of all signals of the educational computer system down to the register transfer level. In the paper is also given a set of laboratory experiments that the students must carry out successfully using the reference manual and the software package as a prerequisite for taking an exam in Computer architecture and organization.

The VSDS environment based laboratory in computer architecture and organisation

Courses in computer architecture and organisation are indispensable part of any computer engineering curriculum. In most of cases these courses include the work in the laboratory with the aim to provide students not only with the theoretical background but also with some practical experience. The article presents an approach of achieving this using the originally developed VSDS environment. The background and motivation leading towards the development of the VSDS environment are first given. Then, the VSDS environment features are briefly described. Finally, the use of the VSDS environment in laboratories for the courses in the logical design of digital systems, the computer architecture and organisation and the design of computer systems is presented.

WASP: A Web-Based Simulator for an Educational Pipelined Processor

This paper presents a web-based simulator for an educational pipelined RISC processor, developed at the Faculty of Electrical Engineering, University of Belgrade. The architecture and organisation of the processor are devised to include typical features of both the RISC architecture and the pipelined organisation. Its graphical simulator makes it possible to follow parts of the processor organisation at both the global level and the register transfer level. The simulator, also, enables the navigation through all parts of the processor, the customisable notifications of significant events during the execution of an instruction and the tracking of relevant values of signals and contents of registers and memory locations. The execution of instructions can be carried out forward one clock or the whole programme and can be returned one clock backward. The simulator is aimed to be used both for exercises in a laboratory and individual student training via the Internet.

A Memory System for Education

The memory system is one of the core topics in computer architecture and organization. An important problem in teaching this topic is how to help students connect their theoretical knowledge of memory system concepts with the practical problems facing the designer of various parts of a memory system. A common approach to tackling this problem is to organize practical exercises in the laboratory using a memory system simulator. The existing simulators mainly focus on subtle memory system issues, such as cache performance, latency, coherence and consistency models in multiprocessor systems and do not admit a view of design details and internal activities within various parts of a memory system. This paper presents an originally developed memory system for education and its web-based simulator. The memory system includes the virtual memory and translation look-aside buffer, the cache memory and the interleaved main memory. The simulator facilitates a web-based clock-by-clock interactive simulation of the memory system, its visual presentation at the register-transfer level and navigation through parts of the system. They can be used for exercises in the laboratory and self-learning from home.