Jpm Jeroen Voeten

Software/Hardware Engineering with the Parallel Object-Oriented Specification Language

The complexity of designing hardware/software systems motivates research on frameworks that structure and automate the design process. Such design methodologies reduce the risk of expensive design-implementation iterations by assisting designers in constructing models. Software/hardware engineering (SHE) is a general-purpose system-level design methodology that supports analysing both functional correctness and performance properties. SHE combines the Unified Modelling Language with the parallel object-oriented specification language to specify models. The designer is assisted in constructing models using these languages and applying the analysis techniques with various guidelines and modelling patterns. A key feature of SHE is its foundation on formal methods, which ensures that the obtained analysis results are unambiguous. SHE also includes guidelines and techniques for automatic synthesis of real-time control software. This is again based on formal methods to ensure that properties in a model (including real-time properties) are preserved by the software realisation. Finally, to enable an effective and efficient application of the modelling languages as well as the analysis and synthesis techniques, SHE is accompanied with a set of user-friendly tools. This paper gives an overview of SHE, thereby briefly touching upon the underlying mathematical foundation of the analysis and synthesis techniques as well as upon some open issues that require further research.

AN ABSTRACT MODELING APPROACH TOWARDS SYSTEM-LEVEL DESIGN-SPACE EXPLORATION

Integration of increasingly complex systems on a chip augments the need of system-level methods for specification and design. In the earliest phases of the design process important design decisions can be taken on the basis of a fast exploration of the design space. This paper describes an abstract modeling approach towards system-level design-space exploration, which is formal and flexible. It uses a uniform system model that contains both functional and architectural information. Disjunct, parameterizable resources represent the real-time behavior of the target architecture. Due to the expressiveness of the modeling language (POOSL), control as well as data oriented behavior can be specified in the functional part of the system model. Well-founded design decisions can be taken as a result of performance estimations that are based on Markov theory.

Using the SHE Method for UML-Based Performance Modeling

The design of complex real-time distributed hardware/software systems commonly involves evaluating the performance of several design alternatives. Early in the design process, it is therefore desirable that design methods support constructing abstract models for the purpose of analysis. Recent extensions to the Unified Modeling Language (UML) that enable specifying schedulability, performance and time provide a means to start developing such models directly after defining the concepts and requirements of a system. However, UML hampers the evaluation of performance properties because this requires constructing executable models with a modeling language that supports application of mathematical analysis techniques. In this paper, we present how the Software/Hardware Engineering (SHE) method can be used for the performance modeling of real-time distributed hardware/software systems. Starting from a UML specification, SHE enables constructing formal executable models based on the expressive modeling language POOSL (Parallel Object-Oriented Specification Language).

A model-driven design approach for mechatronic systems

The software design is one of the most challenging tasks during the design of a mechatronic system. On one hand, it has to provide solutions to deal with concurrency and timeliness issues of the system. On the other hand, it has to glue different disciplines (such as software, control and mechanical) of the system as a whole. In this paper, we propose a model-driven approach to design the software part of a mechatronic system, which consists of two major parts: systematic modeling and correctness-preserving synthesis. The modeling stage is divided into four steps, which focus on different aspects (such as concurrency, multiple disciplines and timeliness) of the system respectively. In particular, we propose a set of handshake patterns to capture the concurrent aspect of the system. These patterns assist designers to build up an adequate top-level model efficiently. Furthermore, they separate the system into a set of concurrent components, each of which can be further refined independently. Subsequently, the multidisciplinary and realtime aspects of the system are naturally specified and analyzed in a series of refinements. After the important aspects of the system are specified and analyzed in a unified model, a software implementation is automatically synthesized from the model, the correctness of which is ensured by construction. The effectiveness of the proposed approach is illustrated by a complex production cell system.

On the fundamental limitations of transformational design

The completeness of a collection of design transformations is an important aspect in transformational design. Completeness guarantees that any correct design can in principle be explored using the transformation system. In the field of transformational design the problem of incompleteness is not well understood and it is often believed that complete transformation systems can be constructed. In this article, we show, using a formal framework based on the theory of computation, that this is not the case if the transformation system is based on an expressive general-purpose design language such as VHDL. Only when restrictions are imposed on the design language and correctness relation, a transformation system can be made complete in theory, but this is expected to result in serious practical problems. It is shown that the incompleteness problem in transformational design is closely related to the syntactic variance problem in high-level synthesis and that this latter problem is not solvable in general either.

Fast Multiprocessor Scheduling with Fixed Task Binding of Large Scale Industrial Cyber Physical Systems

Latest trends in embedded platform architectures show a steady shift from high frequency single core platforms to lower-frequency but highly-parallel execution platforms. Scheduling applications with stringent latency requirements on such multiprocessor platforms is challenging. Our work is motivated by the scheduling challenges faced by ASML, the worlds leading provider of wafer scanners. A wafer scanner is a complex cyber-physical system that manipulates silicon wafers with extreme accuracy at high throughput. Typical control applications of the wafer scanner consist of thousands of precedence-constrained tasks with latency requirements. Machines are customized so that precise characteristics of the control applications to be scheduled and the execution platform are only known during machine start-up. This results in large-scale scheduling problems that need to be solved during start-up of the machine under a strict timing constraint on the schedule delivery time. This paper introduces a fast and scalable static-order scheduling approach for applications with stringent latency requirements and a fixed binding on multiprocessor platforms. It uses a heuristic that makes scheduling decisions based on a new metric to find feasible schedules that meet timing requirements as quickly as possible and it is shown to be scalable to very large task graphs. The computation of this metric exploits the binding information of the application. The approach will be incorporated into the ASMLs latest generation of wafer scanners.

Performance model checking scenario-aware dataflow

Dataflow formalisms are useful for specifying signal processing and streaming applications. To adequately capture the dynamic aspects of modern applications, the formalism of Scenario-Aware Dataflow (SADF) was recently introduced, which allows analysis of worst/best-case and average-case performance across different modes of operation (scenarios). The semantic model of SADF integrates non-deterministic and discrete probabilistic behaviour with generic discrete time distributions. This combination is different from the semantic models underlying contemporary quantitative model checking approaches, which often assume exponentially distributed or continuous time or they lack support for expressing discrete probabilistic behaviour. This paper discusses a model-checking approach for computing quantitative properties of SADF models such as throughput, time-weighted average buffer occupancy and maximum response time. A compositional state-space reduction technique is introduced as well as an efficient implementation of this method that combines model construction with on-the-fly state-space reductions. Strong reductions are possible because of special semantic properties of SADF, which are common to dataflow models. We illustrate this efficiency with several case studies from the multi-media domain.

Modular model-based supervisory controller design for wafer logistics in lithography machines

Development of high-level supervisory controllers is an important challenge in the design of high-tech systems. It has become a significant issue due to increased complexity, combined with demands for verified quality, time to market, ease of development, and integration of new functionality. To deal with these challenges, model-based engineering approaches are suggested as a cost-effective way to support easy adaptation, validation, synthesis, and verification of controllers. This paper presents an industrial case study on modular design of a supervisory controller for wafer logistics in lithography machines. The uncontrolled system and control requirements are modeled independently in a modular way, using small, loosely coupled and minimally restrictive extended finite automata. The multiparty synchronization mechanism that is part of the specification formalism provides clear advantages in terms of modularity, traceability, and adaptability of the model. We show that being able to refer to variables and states of automata in guard expressions and state-based requirements, enabled by the use of extended finite automata, provides concise models. Additionally, we show how modular synthesis allows construction of local supervisors that ensure safety of parts of the system, since monolithic synthesis is not feasible for our industrial case.

Robustness analysis of multiprocessor schedules

Tasks executing on general purpose multiprocessor platforms exhibit variations in their execution times. As such, there is a need to explicitly consider robustness, i.e., tolerance to these fluctuations. This work aims to quantify the robustness of schedules of directed acyclic graphs (DAGs) on multiprocessors by defining probabilistic robustness metrics and to present a new approach to perform robustness analysis to obtain these metrics. Stochastic execution times of tasks are used to compute completion time distributions which are then used to compute the metrics. To overcome the difficulties involved with the max operation on distributions, a new curve fitting approach is presented using which we can derive a distribution from a combination of analytical and limited simulation based results. The approach has been validated on schedules of time-critical applications in ASML wafer scanners.

Predicting Timing Performance of Advanced Mechatronics Control Systems

Embedded control is a key product technology differentiator for many high-tech industries, including ASML. The strong increase in complexity of embedded control systems, combined with the occurrence of late changes in control requirements, results in many timing performance problems showing up only during the integration phase. The fallout of this is extremely costly design iterations, severely threatening the time-to-market and time-to-quality constraints. This paper reports on the industrial application at ASML of the Y-chart method to attack this problem. Through the largely automated construction of executable models of a wafer scanners mechatronics control application and platform, ASML was able to obtain high-level overview early on in the development process. The system wide insight in timing bottlenecks gained this way resulted in more than a dozen improvement proposals yielding significant performance gains. These insights also led to a new development roadmap of the mechatronics control execution platform.