Ju Hee Choi

Selective Access to Filter Cache for Low-Power Embedded Systems

Filter cache has been introduced as one solution of reducing cache power consumption. When the filter cache is utilized in a memory system, more than 50% of the power reduction is accomplished due to the filter cache. However, more than 20% of the performance is compromised as well. To minimize the performance loss of the filter cache, this paper proposes a new filter cache predictor model and its algorithm. In our scheme, Mode Selection Bit (MSB) controls selective accesses to a filter cache and a Branch Target Buffer (BTB). The simulation result shows that our solution provides performance improvement, in energy-delay product, up to about 9.1%, compared to previous policies.

Adaptive cache compression for non-volatile memories in embedded system

Cache compression has been studied to increase the effective cache size by storing the cache blocks in a compressed form in the cache. However, it also generates additional write operations during the compressing and compacting of cache blocks. Since increasing the write operations leads to a surging of dynamic energy consumption and a shortening of the lifetime of the cache in the Non-Volatile Memory (NVM) based Last-Level Cache (LLC), it is needed to balance the extra write operations against the performance improvement. In this paper, we identify that cache compression is not always efficient for NVM-based LLC. In light of the analysis, we propose Adaptive Cache Compression for NVM (ACCNVM) whose cache block is only compressed when cache compression is efficient. The result shows that our proposal achieves a 16.4% energy savings and a 19.1% lifetime extension with respect to the cache, which uses a state-of-the-art cache compression scheme.

Fast Writeable Block-Aware Cache Update Policy for Spin-Transfer-Torque RAM

Spin-transfer-torque RAM (STT-RAM) is one of the emerging nonvolatile memories for last-level cache (LLC) featuring high density and low leakage. However, long latency for the write operation, which comes from the characteristics of nonvolatility, degrades performance when STT-RAM is employed as LLC. To overcome this problem, we revisit the existing cache update policy and propose a new cache update policy to exploit the asymmetric write characteristics of STT-RAM. In our proposal, the data are written into a fast writeable block, regardless of the original position when the block arrives at the LLC. This paper proves the efficiency of our update policy based on analytical models and gives detailed information for implementing the policy. The experimental results show our scheme reduces slow writes by 77.6%, which leads a 31.1% reduction in write latency.

Bypassing method for STT-RAM based inclusive last-level cache

Non-volatile memories (NVMs), such as STT-RAM and PCM, have recently become very competitive designs for last-level caches (LLCs). To avoid cache pollution caused by unnecessary write operations, many cache-bypassing methods have been introduced. Among them, SBAC (a statistics-based cache bypassing method for asymmetric-access caches) is the most recent approach for NVMs and shows the lowest cache access latency. However, SBAC only works on non-inclusive caches, so it is not practical with state-of-the-art processors that employ inclusive LLCs. To overcome this limitation, we propose a novel cache scheme, called inclusive bypass tag cache (IBTC) for NVMs. The proposed IBTC with consideration for the characteristics of NVMs is integrated into LLC to maintain coherence of data in the inclusive LLC with a bypass method and the algorithm is introduced to handle the tag information for bypassed blocks with a minimal storage overhead. Experiments show that IBTC cuts down overall energy consumption by 17.4%, and increases the cache hit rate by 5.1%.

Data filter cache with word selection cache for low power embedded processor

Filter cache was proposed to reduce power consumption. The proposers inserted a small and fast cache, which is called Filter Cache, between core and L1 cache. Filter cache reduced the number of accesses to L1 cache and a significant power savings is achieved. However, because the performance loss is so severe, many researchers should adopt some components which alleviate execution delay. In this paper, we revisit the original filter cache system and identify that employing filter cache does not degrade the system performance in the modern computer system. In base of the analysis, we propose Data Filter Cache system with Word Selection Cache(DWSC) as a new solution. Because tag matching of the L1 cache occurs simultaneously with access to the filter cache, the DWSC does not suffer performance loss. The result shows that our proposal achieves the 75.9% energy savings with respect to the baseline system.

Improving Energy Efficiency and Lifetime of Phase Change Memory using Delta Value Indicator

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.