Ju Sung Park

Design of Digital Audio DSP Core

This paper describes the architecture and design procedure of a DSP (digital signal processor) for the digital audio applications. The suggested DSP has fixed 24bit data structure, 6 stage pipeline, and 127 instructions. Some of the instructions are specially designed for the audio signal processing. Almost instructions are completed within a single cycle. The designed DSP has been verified by comparing the results from CBS (cycle based simulator) and those of HDL simulation through the single instruction set test and the instruction combination test, and real audio applications. Finally, we confirm by the HDL simulation that the DSP carried out successfully out ADPCM and MPEG-2 AAC decoding algorithm. The DSP core is implemented in FPGA using ALTERA Excalibur device and operates at 4MHz.

A cycle accurate model for a DSP

In this paper, we introduce a implementation method and procedural of the CBS (cycle base simulator), cycle accurate simulation model, which describes the operation of a 24 bit DSP (digital signal processor) at a pipeline cycle level. This tool is some functional abstraction and cycle accurate timing model of target DSP. The CBS can show the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The design procedure has been carried out by the following procedure, analysis of target DSP specification, implementation of function block, design of pipeline, design of instruction decoder, and implementation of the instructions. We model the DSP with high level language C++ before the hardware design gets started with HDL to investigate the performance of the DSP. We verified the CBS by running all instructions of DSP and two application programs. The CBS will be used as a reference of logic simulation of the DSP and in RTL model verification under co-simulation environment.