Juan Antonio Clemente

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

New generation embedded systems demand high performance, efficiency, and flexibility. Reconfigurable hardware can provide all these features. However, the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment, task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on as-soon-as-possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.

Efficiently scheduling runtime reconfigurations

Due to the emergence of portable devices that must run complex dynamic applications there is a need for flexible platforms for embedded systems. Runtime reconfigurable hardware can provide this flexibility but the reconfiguration latency can significantly decrease the performance. When dealing with task graphs, runtime support that schedules the reconfigurations in advance can drastically reduce this overhead. However, executing complex scheduling heuristics at runtime may generate an excessive penalty. Hence, we have developed a hybrid design-time/runtime reconfiguration scheduling heuristic that generates its final schedule at runtime but carries out most computations at design-time. We have tested our approach in a PowerPC 405 processor embedded on a FPGA demonstrating that it generates a very small runtime penalty while providing almost as good schedules as a full runtime approach.

A task graph execution manager for reconfigurable multi-tasking systems

Reconfigurable hardware can be used to build multi-tasking systems that dynamically adapt themselves to the requirements of the running applications. This is especially useful in embedded systems, since the available resources are very limited and the reconfigurable hardware can be reused for different applications. In these systems computations are frequently represented as task graphs that are executed taking into account their internal dependencies and the task schedule. The management of the task graph execution is critical for the system performance. In this regard, we have developed two different versions, a software module and a hardware architecture, of a generic task graph execution manager for reconfigurable multi-tasking systems. The second version reduces the run-time management overheads by almost two orders of magnitude. Hence it is especially suitable for systems with exigent timing constraints. Both versions include specific support to optimize the reconfiguration process.

Evidence of the Robustness of a COTS Soft-Error Free SRAM to Neutron Radiation

Radiation tests with 15-MeV neutrons were performed in a COTS SRAM including a new memory cell design combining SRAM cells and DRAM capacitors to determine if, as claimed, it is soft-error free and to estimate upper bounds for the cross-section. These tests led to cross-section values two orders of magnitude below those of typical CMOS SRAMs in the same technology node. MUSCA SEP3 simulations complement these results predicting that only high-energy neutrons ( > 30 MeV) can provoke bit flips in the studied SRAMs. MUSCA SEP3 is also used to investigate the sensitivity of the studied SRAM to radioactive contamination and to compare it with the one of standard CMOS SRAMs. Results are useful to make predictions about the operation of this memory in environments such as avionics.

A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware

Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize the deployment of the hardware cores on the FPGA platform, trying to reduce the reconfiguration overhead while meeting the desired performance. In this paper, we propose a hybrid mapping and scheduling technique for multi-core applications on reconfigurable devices, which exploits the information about the relationships among the application cores to minimize the overhead due to reconfiguration.

A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems

Reconfigurable hardware can be used to build a multi-tasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs and their execution is typically controlled by an embedded processor that schedules the graph execution. In order to improve the efficiency of the system, the scheduler can apply prefetch and reuse techniques that can greatly reduce the reconfiguration latencies. For a processor all these computations represent a heavy computational load that can significantly reduce the system performance. To overcome this problem we have implemented a HW scheduler using reconfigurablere sources. In addition we have implemented both prefetch and replacement techniques that obtain as good results as previous complex SW approaches, while demanding just a few clock cycles to carry out the computations. We consider that the HW cost of the system (in our experiments 3% of a Virtex-II PRO xc2vp30 FPGA) is affordable taking into account the great efficiency of the techniques applied to hide there configuration latency and the negligible run-time penalty introduced by the scheduler computations.

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This article proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This article also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems

This article presents a methodology for building real-time reconfigurable systems that ensures that all the temporal constraints of a set of applications are met while optimizing the utilization of the available reconfigurable resources. Starting from a static platform that meets all the real-time deadlines, our approach takes advantage of runtime reconfiguration in order to reduce the area needed while guaranteeing that all the deadlines are still met. This goal is achieved by identifying which tasks must be always ready for execution in order to meet the deadlines and by means of a methodology that also allows reducing the area requirements.

Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield Neural Network (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non-fault-tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

This paper addresses the problem of reliability and makespan optimization of hardware task graphs in reconfigurable platforms by applying fault tolerance (FT) techniques to the running tasks based on the exploration of the Pareto set of solutions. In the presented solution, in contrast to the existing approaches in the literature, task graph scheduling, tasks parallelism, reconfiguration delay, and FT requirements are taken into account altogether. This paper first presents a model for hardware task graphs, task prefetch and scheduling, reconfigurable computer, and a fault model for reliability. Then, a mathematical model of an integer nonlinear multi-objective optimization problem is presented for improving the FT of hardware task graphs, scheduled in partially reconfigurable platforms. Experimental results show the positive impacts of choosing the FT techniques selected by the proposed solution, which is named Pareto-based. Thus, in comparison to nonfault-tolerant designs or other state-of-the-art FT approaches, without increasing makespan, about 850% mean time to failure (MTTF) improvement is achieved and, without degrading reliability, makespan is improved by 25%. In addition, experiments in fault-varying environments have demonstrated that the presented approach outperforms the existing state-of-the-art adaptive FT techniques in terms of both MTTF and makespan.