Juergen Roeber

Analog computation methods with the help of analog and pseudo-digital carry signals

This work describes new methods of handling ex-ceedings of the supply range in analog computation stages. These are handled as pseudo-digital and analog carry signals and used to regulate the gain of the stage where they occur as well as all computation stages that follow. A complete example for such an analog computation is simulated and presented and critical parts of the architectures are addressed. In addition, more sophisticated extensions are proposed and the “right” way of carry handling is explained for a specific algorithm, together with a discussion of the advantages of different methods for each application.

Frequency synthesizer for digital satellite radio receiving systems

This paper describes the design and verification of phase lock loop (PLL) components within the framework of a front-end for digital satellite radio diversity reception. First, the functionality of the implemented PLL is described by a block diagram. Second, individual PLL components are presented and analysed. Altogether a voltage controlled oscillator (VCO), an automatic amplitude control (AAC), a buffer stage, a TSCP logic as well as a DCVSL-R high-speed by-two-divider, a multi-modulus divider (MMD), and a phase-frequency detector are developed. The frequency tuning range of the PLL is between 4.34 and 4.70 GHz and hence the VCO tuning range has to be around 4 to 5 GHz. Beyond this, the VCOs post-layout phase noise is -100.50 dBc/Hz at 1 MHz under nominal environmental conditions and the post-layout yield analysis predicts 99.773%. Additionally, the VCO and the AAC are connected. Due to that additional AAC feedback circuit, the current consumption as well as the VCO output amplitude decrease. The overall system simulation shows the settling process of the PLL for the tri-state and the five-state mode of the PFD. Finally the VCO performance is compared with other state-of-the-art LC-VCOs.

Integrated diversity front-end for digital satellite radio reception

This paper presents a diversity integrated circuit (IC) for digital satellite radio (SDARS) at 2.3GHz. The IC contains an RF circuit which enables fast adaptive processing of up to three antenna signals for maximum ratio combining in a fast fading scenario. The RF front-end of the diversity system is integrated using 150nm CMOS technology. The phase of each of the three input paths can be adjusted in quantized steps of 45° from 0° to 360°. If the input signal of one path suffers from fading, a single path can be completely turned off for reducing the power consumption. The diversity IC is evaluated by means of laboratory measurements as well as by tests where antenna signals of real fading scenarios are processed using the presented IC. The results show a typical improvement in radio reception of more than a factor of 4 compared to a conventional reception system.

Low-power analog smart camera sensor for edge detection

This work presents an intelligent analog image sensor system for smart camera applications with the need of edge or marker detection. The system consists of a 3×3 read-out CMOS image sensor, an analog Sobel stage and additional circuitry like operational amplifiers and comparators to compute a 1 bit image with the edges present in the taken photo. This information can then be further processed digitally to detect specific shapes in order to control robot routines, for example. The architecture of the proposed system is highly desirable as dedicated analog hardware has significant advantages in terms of power and speed compared to digital implementations. The overall system is simulated with the help of a 3×3 CMOS image sensor IC as well as Cadence Virtuoso for analog circuit simulation and MATLAB to convert the sequential information back to an image, and compared to other state of the art CMOS image sensors with edge detection capability. The analog Sobel circuit runs with a clock of 10 MHz and consumes less than 0.79 mW average power for the computation of the example image, and the whole 200×200 pixel image sensor consumes only 5.5 mW at a frame rate of 75 fps.

A low power CMOS transmitter with Class-E power amplifiers for positioning application in multi-band

In this paper, a transmitter for outdoor positioning application such as animal tracking is introduced. Class-E power amplifiers are exploited in the transmitter system in order to increase the energy efficiency for the demand of long operation duration of the system. Along with the need of power saving, a circuit topology is proposed to realize the modulation based on Binary Offset Carrier (BOC) technique at two different bands to achieve higher positioning accuracy and better utilization of the spectrum by transmitting data simultaneously. The operating frequencies of the system are 868 MHz and 2.4 GHz, and the circuit is designed in 150nm CMOS technology. The Class-E power amplifier shows the broadband characteristics on the power efficiency from 1 to 3GHz while the measured output power is greater than 10 dBm from 1.3 to 2.8 GHz.

A low noise amplifier chain for digital satellite radio applications

This paper contains the development and verification of low noise amplifier stages (LNA) within the framework of a front-end for digital satellite radio diversity receiver operating around 2.3 GHz. First, a low noise high gain LNA is developed to reach the high requirements of satellite radio reception. Therefore a single-ended cascode architecture is chosen. The simulated noise figure is 0.58 dB and the gain is 19.87 dB. Second, a differential stage is designed to fulfill the specification with regards to backward isolation and common-mode rejection. This circuit has a measured gain of 10.15 dB and a backward isolation of -43.24 dB. Furthermore, the two stages are combined by an integrated balun and the overall performance is verified. Due to the good noise performance of the first stage, the overall noise figure is 0.64 dB, the gain is 29.83 dB and the backward isolation is -76.07 dB. All in all the whole circuit has a current consumption of 25.40 mA. Finally the LNA performance is compared with other state-of-the-art LNAs.

A multi-functional reconfigurable low-power ultra-high PSRR CMOS reference-system

This paper presents a new reference system with emphasis on low power design and high power supply rejection. The untrimmed reference provides a 600 mV output voltage, which only differs by 5.75mV in the temperature range between -40°C and +125°C and a PSRR of -157.2dB at 10Hz. The core part of the reference produces a reference potential of 416.1mV with a deviation of only 1.59 mV. Moreover, the circuit provides a 900mV output, a temperature independent 3 μA current and trimming possibilities for the temperature curves and the amplitude of output voltages and currents. Under all operating conditions, the post-layout Corner- and Monte-Carlo-Simulations show a power consumption of less than 40μA and ensure functionality across process, supply voltage and temperature variations.

Area-efficient fully integrated dual-band class-E/F power amplifier with switchable output power for a BPSK/OOK transmitter

This paper presents a novel dual-band class-E/F power amplifier (PA) with switchable output power. It is targeted to work in a BPSK/OOK transmitter in smart facility applications like an autarkic asset-tracking system based on small sensor nodes. The amplifier is fully-integrated and able to operate at both 434 MHz and 868 MHz without the need for additional inductors, making the design very area-efficient. The output power settings at 868 MHz are controllable between −1.79 dBm and −24.61 dBm at 4.96 mA and 1.43 mA current consumption, respectively. The whole circuit including all inductors and the matching network in front of the antenna consumes only 0.9 mm2 chip area and is fully integrated in a 180 nm CMOS process together with a VCO and a PLL.

A combination of a digital foreground and background calibration for a 16 bit and 200MS/s pipeline analog-to-digital converter

High-Performance Analog-to-Digital Converter (ADC) have high requirements concerning sampling rate and linearity. Therefore a new formula is derived to determine, which pipeline stage dependent on the used capacitor sizes needs to be calibrated for the targeted linearity. Furthermore, a model of a 16 bit and 200 MS/s pipeline ADC is described. A combination of a digital foreground and a digital background calibration is presented, which can compensate linear errors and achieves a DNL smaller than ±1 and a THD of −88 dB.

Analog non-linear transformation-based tone mapping for image enhancement in C-arm CT

Flat-Panel C-arm Computed Tomography (CT) suffers from pixel saturation due to the detectors limited dynamic range. We describe a novel approach of analog, non-linear tone mapping (TM) for preventing detector saturation. An analog TM operator (TMO) applies a non-linear transformation in a CMOS (complementary metal-oxide semiconductor) sensor and its inverse TMO based on 14-bit digital raw data. This is done in order to prevent overexposure and to enhance image quality to 32 bits. The method was applied to the cases of low-contrast head imaging and to that of imaging both knees. Cone-beam projection data with and without overexposure was simulated for a 200 degree short-scan of the knees and a 360 degree full-scan of a Forbild head phantom. The results show an increased correlation coefficient with respect to ground truth of 0.99 for TMO compared to 0.96 for overexposed knee data and a higher low-contrast visibility (CC=0.99) compared to linear quantization (CC=0.97).