Julian J. McMorrow

Solution-processed carbon nanotube thin-film complementary static random access memory.

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

Subnanowatt Carbon Nanotube Complementary Logic Enabled by Threshold Voltage Control

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

Ambient-Processable High Capacitance Hafnia-Organic Self- Assembled Nanodielectrics

Ambient and solution-processable, low-leakage, high capacitance gate dielectrics are of great interest for advances in low-cost, flexible, thin-film transistor circuitry. Here we report a new hafnium oxide-organic self-assembled nanodielectric (Hf-SAND) material consisting of regular, alternating π-electron layers of 4-[[4-[bis(2-hydroxyethyl)amino]phenyl]diazenyl]-1-[4-(diethoxyphosphoryl) benzyl]pyridinium bromide) (PAE) and HfO2 nanolayers. These Hf-SAND multilayers are grown from solution in ambient with processing temperatures ≤150 °C and are characterized by AFM, XPS, X-ray reflectivity (2.3 nm repeat spacing), X-ray fluorescence, cross-sectional TEM, and capacitance measurements. The latter yield the largest capacitance to date (1.1 μF/cm(2)) for a solid-state solution-processed hybrid inorganic-organic gate dielectric, with effective oxide thickness values as low as 3.1 nm and have gate leakage <10(-7) A/cm(2) at ±2 MV/cm using photolithographically patterned contacts (0.04 mm(2)). The sizable Hf-SAND capacitances are attributed to relatively large PAE coverages on the HfO2 layers, confirmed by X-ray reflectivity and X-ray fluorescence. Random network semiconductor-enriched single-walled carbon nanotube transistors were used to test Hf-SAND utility in electronics and afforded record on-state transconductances (5.5 mS) at large on:off current ratios (I(ON):I(OFF)) of ~10(5) with steep 150 mV/dec subthreshold swings and intrinsic field-effect mobilities up to 137 cm(2)/(V s). Large-area devices (>0.2 mm(2)) on Hf-SAND (6.5 nm thick) achieve mA on currents at ultralow gate voltages (<1 V) with low gate leakage (<2 nA), highlighting the defect-free and conformal nature of this nanodielectric. High-temperature annealing in ambient (400 °C) has limited impact on Hf-SAND leakage densities (<10(-6) A/cm(2) at ±2 V) and enhances Hf-SAND multilayer capacitance densities to nearly 1 μF/cm(2), demonstrating excellent compatibility with device postprocessing methodologies. These results represent a significant advance in hybrid organic-inorganic dielectric materials and suggest synthetic routes to even higher capacitance materials useful for unconventional electronics.

Radiation Effects in Single-Walled Carbon Nanotube Thin-Film-Transistors

The fabrication, characterization, and radiation response of single-walled carbon nanotube (SWCNT) thin-film field effect transistors (SWCNT-TFTs) has been performed. SWCNT-TFTs were fabricated on SiO2-Si substrates from 98% pure semiconducting SWCNTs separated by density gradient ultracentrifugation. Optical and Raman characterization, in concert with measured drain current Ion/Ioff ratios, up to 104, confirmed the high enrichment of semiconducting-SWCNTs. Total ionizing dose (TID) effects, up to 10 MRads, were measured in situ for a SWCNT-TFT under static vacuum. The results revealed a lateral translation of the SWCNT-TFT transfer characteristics to negative gate bias resulting from hole trapping within the SiO2 and SiO2-SWCNT interface. Additional TID exposure conducted in air on the same device had the opposite effect, shifting the transfer characteristics to higher gate voltage, and increasing the channel conductance. No significant change was observed in the device mobility or the SWCNT Raman spectra following a TID exposure of 10 Mrad(Si), indicating extrinsic factors dominate the transfer characteristics in the SWCNT-TFT devices during irradiation. The extrinsic effects of charge trapping and the role that gas adsorption plays in the radiation response are discussed.

Total Ionizing Dose Induced Charge Carrier Scattering in Graphene Devices

We investigate total ionizing dose (TID) effects in graphene field effect transistors comprised of chemical vapor deposition grown graphene transferred onto trimethylsiloxy(TMS)-passivated SiO2 Si substrates. TID exposure with a positive gate bias increases the concentration of positive oxide trapped charges near the SiO2/TMS/graphene interface making Coulomb-potential scatterer limited mobility more apparent. In particular, we observe asymmetric degradation in electron and hole mobility, the former degrading more rapidly. Consistent with the electron-hole puddle description, we observe an increase in intrinsic electron carrier density that varies linearly with the oxide trapped charge density, while the hole carrier density remains largely unaltered. These effects give rise to an increasing minimum conductivity.

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10−5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Charge injection in high-κ gate dielectrics of single-walled carbon nanotube thin-film transistors.

We investigate charge injection into the gate dielectric of single-walled carbon nanotube thin-film transistors (SWCNT-TFTs) having Al(2)O(3) and HfO(2) gate dielectrics. We demonstrate the use of electric field gradient microscopy (EFM) to identify the sign and approximate the magnitude of the injected charge carriers. Charge injection rates and saturation levels are found to differ between electrons and holes and also vary according to gate dielectric material. Electrically, Al(2)O(3) gated devices demonstrate smaller average hysteresis and notably higher average on-state current and p-type mobility than those gated by HfO(2). These differences in transfer characteristics are attributed to the charge injection, observed via EFM, and correlate well with differences in tunneling barrier height for electrons and holes formed in the conduction and valence at the SWCNT/dielectric interface, respectively. This work emphasizes the need to understand the SWCNT/dielectric interface to overcome charge injection that occurs in the focused field region adjacent to SWCNTs and indicates that large barrier heights are key to minimizing the effect.

Layer‐by‐Layer Assembled 2D Montmorillonite Dielectrics for Solution‐Processed Electronics

Layer-by-layer assembled 2D montmorillonite nanosheets are shown to be high-performance, solution-processed dielectrics. These scalable and spatially uniform sub-10 nm thick dielectrics yield high areal capacitances of ≈600 nF cm(-2) and low leakage currents down to 6 × 10(-9) A cm(-2) that enable low voltage operation of p-type semiconducting single-walled carbon nanotube and n-type indium gallium zinc oxide field-effect transistors.

Chemical vapor deposition of monolayer MoS2 directly on ultrathin Al2O3 for low-power electronics

Monolayer MoS2 has recently been identified as a promising material for high-performance electronics. However, monolayer MoS2 must be integrated with ultrathin high-κ gate dielectrics in order to realize practical low-power devices. In this letter, we report the chemical vapor deposition (CVD) of monolayer MoS2 directly on 20 nm thick Al2O3 grown by atomic layer deposition (ALD). The quality of the resulting MoS2 is characterized by a comprehensive set of microscopic and spectroscopic techniques. Furthermore, a low-temperature (200 °C) Al2O3 ALD process is developed that maintains dielectric integrity following the high-temperature CVD of MoS2 (800 °C). Field-effect transistors (FETs) derived from these MoS2/Al2O3 stacks show minimal hysteresis with a sub-threshold swing as low as ∼220 mV/decade, threshold voltages of ∼2 V, and current ION/IOFF ratio as high as ∼104, where IOFF is defined as the current at zero gate voltage as is customary for determining power consumption in complementary logic circuits....

Tunable Radiation Response in Hybrid Organic–Inorganic Gate Dielectrics for Low-Voltage Graphene Electronics

Solution-processed semiconductor and dielectric materials are attractive for future lightweight, low-voltage, flexible electronics, but their response to ionizing radiation environments is not well understood. Here, we investigate the radiation response of graphene field-effect transistors employing multilayer, solution-processed zirconia self-assembled nanodielectrics (Zr-SANDs) with ZrOx as a control. Total ionizing dose (TID) testing is carried out in situ using a vacuum ultraviolet source to a total radiant exposure (RE) of 23.1 μJ/cm(2). The data reveal competing charge density accumulation within and between the individual dielectric layers. Additional measurements of a modified Zr-SAND show that varying individual layer thicknesses within the gate dielectric tuned the TID response. This study thus establishes that the radiation response of graphene electronics can be tailored to achieve a desired radiation sensitivity by incorporating hybrid organic-inorganic gate dielectrics.