Julien Sylvestre

Underfill delamination to chip sidewall in advanced flip chip packages

A number of failure mechanisms related to the underfill material in flip chip plastic ball grid array packages are well documented in the literature (underfill-to-chip passivation delamination, underfill-to-substrate soldermask delamination, chip cracking, interconnect fatigue, etc.). This paper discusses the delamination of the underfill from the chip sidewalls, another failure mechanism which has become more prevalent with component material changes, increases in die dimensions, finer C4 pitches and substrates with larger coefficient of thermal expansion. A detailed study is presented for the initiation of underfill-to-sidewall delamination, based on experimental data as well as finite element modeling. It is shown generally that both stress at the chip-underfill interface near the chip corner, and poor adhesion of the underfill to the chip sidewalls contribute to the initiation of underfill delaminations. Various parameters influencing stress (package design, underfill material thermo-mechanical properties) and adhesion (underfill base chemistry and additives, filler treatment, chip sidewall cleanliness) are discussed.

Simulations of laser locking to a LISA arm

We present detailed numerical simulations of a laser phase stabilization scheme for Laser Interferometer Space Antenna (LISA), where both lasers emitting along one arm are locked to each other. Including the standard secondary noises and spacecraft motions that approximately mimic LISAs orbit (excluding the rotation of the constellation), we verify that very stable laser phases can be obtained and that time delay interferometry can be used to remove the laser phase noise from measurements of gravitational wave strains. Most importantly, we show that this locking scheme can provide significant simplifications over LISAs baseline design in the implementation of time delay interferometry.

From Leaded to Lead Free Assembly and New Packaging Technology Challenges

The migration to lead free connections in the microelectronic industry has brought forth many technical challenges, especially in the packaging technology area with respect to materials and processes. The two major drivers to these challenges are the higher melting point and the thermo-mechanical behaviour (less creep than SnPb alloy) of the replacement alloy. The higher melting point drives higher reflow temperatures during the packaging assembly as well as the card assembly and this requires the use of new materials. Higher stresses in the package can result in a reliability impact for the product. The challenge of these lead free related changes is exacerbated by other trends in leading edge organic packaging such as chip low K dielectric materials, larger package and larger chip dimensions and, reduced chip bump pitch. This paper provides the reliability results obtained through various lead free organic package test matrices and qualifications. The principal failure mechanisms are presented and are explained through material properties and finite element modeling studies. Details of the package technology qualification process and results are presented.

Vibrations in the Flip-Chip Soldering Process

General results are presented for the dynamics of all six degrees of freedom of a rigid flip-chip device connected by an array of melted solder joints to a substrate subjected to small stationary random accelerations. The solder joints are modeled as dissipative fluid members which develop a linear restoring force when displaced in the horizontal or vertical directions. The parameters for this model (stiffness and damping of the melted joints) are obtained experimentally by measuring the resonant behavior of a device oscillating in the out-of-plane direction. A quantitative model is constructed for an arbitrary device for the statistics of the translational degrees of freedom, rotational degrees of freedom, and solder joint deformations.

Computing with networks of nonlinear mechanical oscillators

As it is getting increasingly difficult to achieve gains in the density and power efficiency of microelectronic computing devices because of lithographic techniques reaching fundamental physical limits, new approaches are required to maximize the benefits of distributed sensors, micro-robots or smart materials. Biologically-inspired devices, such as artificial neural networks, can process information with a high level of parallelism to efficiently solve difficult problems, even when implemented using conventional microelectronic technologies. We describe a mechanical device, which operates in a manner similar to artificial neural networks, to solve efficiently two difficult benchmark problems (computing the parity of a bit stream, and classifying spoken words). The device consists in a network of masses coupled by linear springs and attached to a substrate by non-linear springs, thus forming a network of anharmonic oscillators. As the masses can directly couple to forces applied on the device, this approach combines sensing and computing functions in a single power-efficient device with compact dimensions.

Thermal and mechanical analysis of a concentrated photovoltaic module with integrated secondary optics

The behavior of the thermal and mechanical stresses in CPV modules with integrated secondary optics (SOE) is studied. The aim of this study is to develop a numerical platform for the validation of CPV module designs. The study is based on numerical simulations using the finite elements methods. A comprehensive and complete numerical model is constructed using modeling software and methodologies initially developed to study the reliability of microelectronic components. Thermal analysis results show that most of the heat is dissipated in the downward direction, through the module substrate. This means that attaching the SOE to the solar cell with a layer of material that has a low thermal conductivity (such as silicone) is not harmful to the overall module thermal performances. In addition, the presence of the SOE does not subject the cell to compressive stresses due to the layer of silicone that acts as a stress buffer. The maximum strains are located in the connecting elements (e.g. silicone between SOE ...

Modeling the Flip-Chip Wetting Process

A numerical model is presented for the portion of the flip-chip joining process where liquid-state solder bumps on the substrate and on the device merge (wet) to form full interconnections. An excellent agreement is demonstrated between calculations and experimental data for the accompanying reduction as a function of time in the device-substrate gap height resulting from the wetting process. The model is based on the detailed description of the random wetting transition of every interconnection in large devices, parametrized by a single parameter describing the wetting dynamics of the solder (including, for instance, the retarding effect of oxidation). This allows the model to be used to systematically study the effect of a number of variables (thermal expansion and heating rates, substrate warpage, spatial distribution of solder bump volumes on the substrate and device, etc.) on the rate of occurrence of important defects that appear during the flip-chip wetting process, such as electrical open (nonwet) or short (bridge) defects.

Large-Scale Model of Flip-Chip Joining Defects

A numerical model is developed for the flip chip reflow process, including many significant aspects of the joining dynamics: thermal expansion of the device and substrate; temperature-dependent substrate warpage; random variations of the solder volume with position; and global device position above the substrate. A detailed micro-model of each interconnect captures the transition from two contacting solder bumps to a single continuous solder interconnect, using a random wetting delay parameterized by the surface energy of the bumps relative to an energy scale. The model is shown to correctly fit measurements of the device position during the reflow process, and is used to study the occurrence of non-wet and bridge defects. The effects of spatial variations in the solder volume distribution on these defects is studied in details for an actual device with 12 504 interconnections, using an effective data reduction technique.Copyright

Reservoir computing with a single delay-coupled non-linear mechanical oscillator

Reservoir computing was achieved by constructing a network of virtual nodes multiplexed in time and sharing a single silicon beam exhibiting a classical Duffing non-linearity as the source of nonlinearity. The delay-coupled electromechanical system performed well on time series classification tasks, with error rates below 0.1% for the 1st, 2nd, and 3rd order parity benchmarks and an accuracy of ( 78 ± 2 ) % for the TI-46 spoken word recognition benchmark. As a first demonstration of reservoir computing using a non-linear mass-spring system in MEMS, this result paves the way to the creation of a new class of compact devices combining the functions of sensing and computing.Reservoir computing was achieved by constructing a network of virtual nodes multiplexed in time and sharing a single silicon beam exhibiting a classical Duffing non-linearity as the source of nonlinearity. The delay-coupled electromechanical system performed well on time series classification tasks, with error rates below 0.1% for the 1st, 2nd, and 3rd order parity benchmarks and an accuracy of ( 78 ± 2 ) % for the TI-46 spoken word recognition benchmark. As a first demonstration of reservoir computing using a non-linear mass-spring system in MEMS, this result paves the way to the creation of a new class of compact devices combining the functions of sensing and computing.

Study of Capillary Underfill Filler Separation in Advanced Flip Chip Packages

The key role that underfill materials play in highly reliable, advanced flip chip organic packages has generated an increased focus on their behavior and structure. One such behavior relates to the observation of filler separation from the resin matrix which, to date, has been predominantly attributed to gravity or capillary flow. The phenomenon of silica filler separation is discussed in the context of fine pitch, lead-free solder joints with copper-base (pedestal or pillar) under bump metallization and large die packages. The principle mechanism driving filler separation in these structures was confirmed as a migration of the electrostatically charged filler particles away from the copper regions and towards the solder regions of the interconnect. Based on this finding, various factors that influence the surface of the interconnects or the nature and the mobility of the filler particles during the bond and assembly process were explored. It was found that the oxide states and contact angles of the interconnect surfaces do not appear to impact the degree of filler separation. Within the range explored, average filler particle size is ineffective in changing the separation behavior. On the other hand, lower filler content somewhat increases the extent of separation and is believed to be related to an increase in particle mobility. Assembly process variables with known effects on surface interactions and underfill flow were also studied, revealing no observable shift in the occurrence of filler separation. Finally, and most importantly, a reliability study was conducted to investigate the impact of this phenomenon in a very large die (23 × 23 mm2) flip chip organic package subjected to a high level of thermomechanical stress. Using extended Deep Thermal Cycling to 2000 cycles (as opposed to the standard 1000 cycle criterion), no packaging failures occurred and no signs of interconnect degradation were observed. These results are consistent with finite element modeling of the tested package, which showed that stress changes from filler separation in regions of similar dimensions to those that were experimentally observed were within the limits of model error and typical manufacturing variability.