Julio Sahuquillo

Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors

Current microprocessors are based in complex designs, integrating different components on a single chip, such as hardware threads, processor cores, memory hierarchy or interconnection networks. The permanent need of evaluating new designs on each of these components motivates the development of tools which simulate the system working as a whole. In this paper, we present the Multi2Sim simulation framework, which models the major components of incoming systems, and is intended to cover the limitations of existing simulators. A set of simulation examples is also included for illustrative purposes.

Euro-Par 2012: Parallel Processing Workshops

Cloud computing is becoming increasingly popular and prevalent in many domains. However, there is high variability in the programming models, access methods, and operational aspects of different clouds, diminishing the viability of cloud computing as a true utility. Our ADAPAS project attempts to analyze the commonalities and differences between cloud offerings with a view to determining the extent to which they may be unified. We propose the concept of dynamic adapters supported by runtime systems for environment preconditioning, that help facilitate cross platform deployment of cloud applications. This vision paper outlines the issues involved, and presents preliminary ideas for enhancing the executability of applications on different cloud platforms.

A simple power-aware scheduling for multicore systems when running real-time applications

High-performance microprocessors, e.g., multithreaded and multicore processors, are being implemented in embedded real-time systems because of the increasing computational requirements. These complex microprocessors have two major drawbacks when they are used for real-time purposes. First, their complexity difficults the calculation of the WCET (worst case execution time). Second, power consumption requirements are much larger, which is a major concern in these systems. In this paper we propose a novel soft power-aware real-time scheduler for a state-of-the-art multicore multithreaded processor, which implements dynamic voltage scaling techniques. The proposed scheduler reduces the energy consumption while satisfying the constraints of soft real-time applications. Different scheduling alternatives have been evaluated, and experimental results show that using a fair scheduling policy, the proposed algorithm provides, on average, energy savings ranging from 34% to 74%.

A user-focused evaluation of web prefetching algorithms

Web prefetching mechanisms have been proposed to benefit web users by hiding the download latencies. Nevertheless, to the knowledge of the authors, there is no attempt to compare different prefetching techniques that consider the latency perceived by the user as the key metric. The lack of performance comparison studies from the users perspective has been mainly due to the difficulty to accurately reproduce the large amount of factors that take part in the prefetching process, ranging from the environment conditions to the workload. This paper is aimed at reducing this gap by using a cost-benefit analysis methodology to fairly compare prefetching algorithms from the users point of view. This methodology has been used to configure and compare five of the most used algorithms in the literature under current and old workloads. In this paper, we analyze the perceived latency versus the traffic increase (both in bytes and in objects) to evaluate the benefits from the users perspective. In addition, we also analyze the performance results from the prediction point of view to provide insights on the observed performance. Results show that higher algorithm complexity does not improve performance, object-based algorithms outperform those based on pages, and performance among object-based algorithms present minor differences in the object traffic increase.

Exploiting temporal locality in drowsy cache policies

Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage of the overall microprocessor die area. Therefore, recent research has concentrated on the reduction of leakage current dissipated by caches. The variety of techniques to control current leakage can be classified as non-state preserving or state preserving. Non-state preserving techniques power off selected cache lines while state preserving place selected lines into a low-power state. Drowsy caches are a recently proposed state-preserving technique. In order to introduce low performance overhead, drowsy caches must be very selective on which cache lines are moved to a drowsy statePast research on cache organization has focused on how best to exploit the temporal locality present in the data stream. In this paper we propose a novel drowsy cache policy called Reuse Most Recently used On (RMRO), which makes use of reuse information to trade off performance versus energy consumption. Our proposal improves the hit ratio for drowsy lines by about 67%, while reducing the power consumption by about 11.7% (assuming 70nm technology) with respect to previously proposed drowsy cache policies.

Web prefetching performance metrics: a survey

Web prefetching techniques have been pointed out to be especially important to reduce perceived web latencies and, consequently, an important amount of work can be found in the open literature. But, in general, it is not possible to do a fair comparison among the proposed prefetching techniques due to three main reasons: (i) the underlying baseline system where prefetching is applied differs widely among the studies; (ii) the workload used in the presented experiments is not the same; (iii) different performance key metrics are used to evaluate their benefits.This paper focuses on the third reason. Our main concern is to identify which are the meaningful indexes when studying the performance of different prefetching techniques. For this purpose, we propose a taxonomy based on three categories, which permits us to identify analogies and differences among the indexes commonly used. In order to check, in a more formal way, the relation between them, we run experiments and estimate statistically the correlation among a representative subset of those metrics. The statistical results help us to suggest which indexes should be selected when performing evaluation studies depending on the different elements in the considered web architecture.The choice of the appropriate key metric is of paramount importance for a correct and representative study. As our experimental results show, depending on the metric used to check the system performance, results cannot only widely vary but also reach opposite conclusions.

The Impact of the Web Prefetching Architecture on the Limits of Reducing User's Perceived Latency

Web prefetching is a technique that has been researched for years to reduce the latency perceived by users. For this purpose, several Web prefetching architectures have been used, but no comparative study has been performed to identify the best architecture dealing with prefetching. This paper analyzes the impact of the Web prefetching architecture focusing on the limits of reducing the users perceived latency. To this end, the factors that constrain the predictive power of each architecture are analyzed and these theoretical limits are quantified. Experimental results show that the best element of the Web architecture to locate a single prediction engine is the proxy, whose implementation could reduce the perceived latency up to 67%. Schemes for collaborative predictors located at diverse elements of the Web architecture are also analyzed. These predictors could dramatically reduce the perceived latency, reaching a potential limit of about 97% for a mixed proxy-server collaborative prediction engine

An hybrid eDRAM/SRAM macrocell to implement first-level data caches

SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been embedded in logic-based technology, thus overcoming the speed limit of typical DRAM cells. In this paper we propose an n-bit macrocell that implements one static cell, and n-1 dynamic cells. This cell is aimed at being used in an n-way set-associative first-level data cache. Our study shows that in a four-way set-associative cache with this macrocell compared to an SRAM based with the same capacity, leakage is reduced by about 75% and area more than half with a minimal impact on performance. Architectural mechanisms have also been devised to avoid refresh logic. Experimental results show that no performance is lost when the retention time is larger than 50 K processor cycles. In addition, the proposed delayed writeback policy that avoids refreshing performs a similar amount of writebacks than a conventional cache with the same organization, so no power wasting is incurred.

DDG: An Efficient Prefetching Algorithm for Current Web Generation

Web prefetching is one of the techniques proposed to reduce users perceived latencies in the World Wide Web. The spatial locality shown by users accesses makes it possible to predict future accesses based on the previous ones. A prefetching engine uses these predictions to prefetch the Web objects before the user demands them. The existing prediction algorithms achieved an acceptable performance when they were proposed but the high increase in the amount of embedded objects per page has reduced their effectiveness in the current Web. In this paper we show that most of the predictions made by the existing algorithms are useless to reduce the users perceived latency because these algorithms do not take into account how current Web pages are structured, i.e., an HTML object with several embedded objects. Thus, they predict the accesses to the embedded objects in an HTML after reading the HTML itself. For this reason, the prediction advance is not enough to prefetch the objects and therefore there is no latency reduction. As a result of a wide analysis of the behaviour of the most commonly used algorithms, in this paper we present the DDG algorithm that distinguishes between container objects (HTML) and embedded objects to create a new prediction model according to the structure of the current Web. Results show that, for the same amount of extra requests to the server, DDG always outperforms the existing algorithms by reducing the perceived latency between 15% and 150% more without increasing the computing complexity

Dweb model: Representing Web 2.0 dynamism

Due to the increase in the number and popularity of applications such as e-commerce or on-line booking systems, typical of the Web 2.0, dynamic contents are becoming more and more frequent. This trend suggests the review of widely accepted paradigms and models for the World Wide Web. As a system that is continuously changing, both in the offered applications and in its infrastructure, performance evaluation studies are a main concern to provide sound proposals when designing new web-related systems. Although the dynamism in the workload characterization has also been tackled in previous research, it has not been modeled in a precise way yet because of its complex nature. In this paper we propose the Dweb model which represents the dynamism of current web applications in the workload characterization. Dweb is based on three main concepts that allow to model dynamic workload: navigation, workload test and workload distribution. In addition, a dynamic workload generator has been implemented to show the practical application of the proposed model, which has been illustrated through a case study.