Julius Georgiou

Detection of epileptic electroencephalogram based on Permutation Entropy and Support Vector Machines

The electroencephalogram (EEG) has proven a valuable tool in the study and detection of epilepsy. This paper investigates for the first time the use of Permutation Entropy (PE) as a feature for automated epileptic seizure detection. A Support Vector Machine (SVM) is used to classify segments of normal and epileptic EEG based on PE values. The proposed system utilizes the fact that the EEG during epileptic seizures is characterized by lower PE than normal EEG. It is shown that average sensitivity of 94.38% and average specificity of 93.23% is obtained by using PE as a feature to characterize epileptic and seizure-free EEG, while 100% sensitivity and specificity were also obtained in single-trial classifications.

Towards fast solid state DNA sequencing

The current most widely used method for DNA sequencing is the chain termination method or Sanger technique. Many attempts are being made to improve upon this method particularly with regard to the elimination of the latter stage of electrophoresis. Using the ion sensitive field effect transistor and low power signal processing techniques, the possibility of intelligent solid state DNA sequencing is explored.

A Novel Wide-Temperature-Range, 3.9 ppm/

This paper presents an innovative CMOS Bandgap Reference Generator topology that leads to an improved curvature compensation method over a very wide temperature range. The proposed design was implemented in a standard 0.35 μm CMOS process. The compensation is performed by using only poly-silicon resistors. This is achieved by using a second Op-amp that generates a CTAT current, which is subsequently used to enhance the curvature compensation method. The performance of the circuit was verified experimentally. Measured results have shown temperature coefficients as low as 3.9 ppm/^°C over a temperature range of 165^°C ( -15^°C to 150^°C ) and temperature coefficients as low as 13.7 ppm/^°C over an extended temperature range of 200^°C (-50^°C to 150^°C ). In addition the circuit demonstrated very good line regulation performance for a broad range of supply voltages. The measured line regulation at room temperature is 0.039% V.

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A single-chip speech processor/stimulator is presented for use in a totally implanted cochlear prosthesis system. It implements a continuous interleaved sampling (CIS) strategy. By combining the speech processor and the stimulator into one mixed-signal chip, both size and power are reduced sufficiently, so as to make a totally implanted system feasible. First silicon has been validated and typically operates at 126 /spl mu/W (excluding cochlear stimulation currents).

C CMOS Bandgap Reference Circuit

This paper describes a novel partial-current-steering stimulation circuit for implantable vestibular prostheses. The drive hardware momentarily delivers a charge-balanced asymmetric stimulus to a dummy load before steering towards the stimulation electrodes. In this fashion, power is conserved while still gaining from the benefits of current steering. The circuit has been designed to be digitally programmable as part of an implantable vestibular prosthesis. The hardware has been implemented in AMS 0.35 mum 2P4M CMOS technology.

A 126-/spl mu/W cochlear chip for a totally implantable system

We present a design framework for neuromorphic architectures in the nano-CMOS era. Our approach to the design of spiking neurons and STDP learning circuits relies on parallel computational structures where neurons are abstracted as digital arithmetic logic units and communication processors. Using this approach, we have developed arrays of silicon neurons that scale to millions of neurons in a single state-of-the-art Field Programmable Gate Array (FPGA). We demonstrate the validity of the design methodology through the implementation of cortical development in a circuit of spiking neurons, STDP synapses, and neural architecture optimization.

A Partial-Current-Steering Biphasic Stimulation Driver for Vestibular Prostheses

In this paper, we present an architecture and corresponding analysis for large-scale neuromorphic systems using a digital approach where neurons are abstracted as arithmetic logic units and communication processors. After presenting the architecture, we establish a few basic architectural principles, particularly the scaling of the system to large arrays. We demonstrate the reality of a single chip million neuron system built from these principles in commercial off the shelf FPGA.

2013 Special Issue: Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization

This work proposes the use of Permutation Entropy (PE), a measure of time-series complexity, to characterize electroencephalogram (EEG) signals recorded during sleep. Such a measure could provide information concerning the different sleep stages and, thus, be utilized as an additional aid to obtain sleep staging information. PE has been estimated for artifact-free 30s segments from more than 80 hours of EEG records obtained from 16 subjects during all-night recordings, from which the mean PE for each sleep stage was obtained. It was found that different sleep stages are characterized by significantly different PE values, which track the physiological changes in the complexity of the EEG signals observed at the different sleep stages. This finding encourages the use of PE as an additional aide to either visual or automated sleep staging.

Design of a one million neuron single FPGA neuromorphic system for real-time multimodal scene analysis

Background General anesthesia is a reversible state of unconsciousness and depression of reflexes to afferent stimuli induced by administration of a “cocktail” of chemical agents. The multi-component nature of general anesthesia complicates the identification of the precise mechanisms by which anesthetics disrupt consciousness. Devices that monitor the depth of anesthesia are an important aide for the anesthetist. This paper investigates the use of effective connectivity measures from human electrical brain activity as a means of discriminating between ‘awake’ and ‘anesthetized’ state during induction and recovery of consciousness under general anesthesia. Methodology/Principal Findings Granger Causality (GC), a linear measure of effective connectivity, is utilized in automated classification of ‘awake’ versus ‘anesthetized’ state using Linear Discriminant Analysis and Support Vector Machines (with linear and non-linear kernel). Based on our investigations, the most characteristic change of GC observed between the two states is the sharp increase of GC from frontal to posterior regions when the subject was anesthetized, and reversal at recovery of consciousness. Features derived from the GC estimates resulted in classification of ‘awake’ and ‘anesthetized’ states in 21 patients with maximum average accuracies of 0.98 and 0.95, during loss and recovery of consciousness respectively. The differences in linear and non-linear classification are not statistically significant, implying that GC features are linearly separable, eliminating the need for a complex and computationally expensive non-linear classifier. In addition, the observed GC patterns are particularly interesting in terms of a physiological interpretation of the disruption of consciousness by anesthetics. Bidirectional interaction or strong unidirectional interaction in the presence of a common input as captured by GC are most likely related to mechanisms of information flow in cortical circuits. Conclusions/Significance GC-based features could be utilized effectively in a device for monitoring depth of anesthesia during surgery.

The use of permutation entropy to characterize sleep electroencephalograms.

In this paper a basic, four-transistor, resistorless current reference circuit is described, aimed at implantable biomedical applications. The circuit takes advantage of two different thickness thermally grown gate oxides, which are available in most high voltage processes and in some of the latest sub-micron feature size processes. Current tuning is achieved by sizing the transistors accordingly.