Jun Rim Choi

Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm

In this paper, two implementation methods to optimize a 1024-bit RSA processor are presented. The Montgomery algorithm is used and modified considering large bit modular multiplication. We propose two architectures for 1024-bit RSA processing in order to reduce the required hardware resources and to achieve speed improvement. One reduces the hardware resources using the L-R (left to right) binary method, and the other achieves speed improvement using the R-L (right to left) binary method. We have implemented two single-chip 1024-bit RSA processors based on the proposed architectures in 0.5-/spl mu/m SOG technology using Verilog-HDL. As a result, it is shown that each architecture contributes to speed improvement and area saving.

An efficient implementation of hash function processor for IPSEC

This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-specd cryptographic accelcrators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Intemet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-I, HAS-I60 and MDS in one chip. These hash algorithms are designed to reduce the number of gates. SHA-I module is combined with HAS-I60 module. As the result. thc required logic elements are reduced by 27%. These hash algorithms have been implemented using Alteras EP20K1000EBCh52-3 with PCI bus interface.

A modified two-step SOVA-based turbo decoder with a fixed scaling factor

In this paper, two optimum implementation schemes are proposed in soft output Viterbi algorithm (SOVA) with high performance. One is modifying the architecture known as two-step SOVA scheme in order to obtain high speed. The other is lowering the reliability values to a same level with a scaling factor 0.25 or 0.33 for hardware implementation in order to compensate for the distortion. Also, we have implemented one step SOVA and the modified architecture for comparison of two schemes with 0.65 /spl mu/m Samsung SOG technology using Verilog HDL. At result, The modified architecture provides higher SNR performance by 2 dB at the BER 1E-04 than that of the general SOVA. Also we have obtained good performance by using a fixed scaling factor, by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to high performance.

A modified two-step SOVA-based turbo decoder for low power and high performance

In this paper two methods for low power and high performance are proposed for the soft output Viterbi algorithm (SOVA). One is to employ a modified architecture using a combination of a trace back (TB) for finding survivor states and a double trace back for finding the weight in two-step SOVA. The other is to lower the reliability values to the same level as a scaling factor to compensate for the distortion brought by overestimating those values in the original SOVA. We introduce a fixed scaling factor 0.25 or 0.33 for a rate 1/3 and 8-state turbo decoder with a 256-bit frame in hardware implementation to lower the reliability values. The modified architecture used in two-step SOYA allows important savings in area and power dissipation, compared with those of one-step (register exchange (RE) or TB) SOVA, and it also provides higher SNR performance (2 dB at the BER IE-04) than that of the conventional SOVA. Good performance is obtained by using a fixed scaling factor by which the soft output of SOVA can be considered as being multiplied. The simulation results show that the modified architecture with both methods contributes to low power and high performance.

A Parity Checker for a Large RNS Numbers Based on Montgomery Reduction Method

Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2 r - (2 t ± 1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number, The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.

Compatible design of CCMP and OCB AES cipher for wireless LAN security

We propose a compatible design of CCMP and OCB AES cipher for wireless LAN. IEEE 802.11i defines the AES-based cipher system, which is operated in CCMP mode or in OCB mode. Our design supports both modes of operation. The implemented OCB and CCMP feature 40 Mbps and 243 Mbps throughput, respectively, at 50 MHz frequency, and are targeted to a Xilinx Vertex FPGA device.

Neural network-based scalable fast intra prediction algorithm in H.264 encoder

In this paper, we propose a neural network-based scalable fast intra prediction algorithm in H.264 in order to reduce redundant calculation time by selecting the best mode of 4x 4 and 16x 16 intra prediction. In this reason, it is possible to encode compulsively by 4 X 4 intra prediction mode for current MB(macro block)s best prediction mode without redundant mode decision calculation in accordance with neural networks output resulted from co-relation of adjacent encoded four left, up-left, up and up-right blocks. If there is any one of MBs encoded by 16x 16 intra prediction among four MBs adjacent to current MB, the probability of re-prediction into 16X 16 intra prediction will become high. We can apply neural networks in order to decide whether to force into 4 X 4 intra prediction mode or not. We can also control both the bit rates and calculation time by modulating refresh factors and weights of neural networks output depend on error back-propagation, which is called refreshing. In case of encoding several video sequences by the proposed algorithm, the total encoding time of 30 input I frames are reduced by 20% ∼ 65% depending upon the test vector compared with JM 8.4 by using neural networks and by modulating scalable refreshing factor. On the other hand, total encoding bits are increased by 0.8% ∼ 2.0% at the cost of reduced SNR of 0.01 dB.