Jun Yu

Formation and characteristics of Pb(Zr,Ti)O3 field-effect transistor with a SiO2 buffer layer

Ferroelectric heterostructures of Au/Pb(Zr0.52Ti0.48)O3/SiO2/Si and Au/Pb(Zr0.52Ti0.48)O3/Si have been fabricated by using laser ablation technique. Electrical properties of these ferroelectric field-effect transistors have been characterized through both the current vs voltage and capacitance vs voltage (C–V) measurements. The C–V characteristics of Au/Pb(Zr0.52Ti0.48)O3/SiO2/Si heterostructures demonstrate a polarization switching behavior, showing a memory window as much as 1 V at 1 kHz. In addition, the experimental results reveal that a SiO2 buffer layer is essential for memory properties in the Au/Pb(Zr0.52Ti0.48)O3/SiO2/Si gate structure.

Preparation and ferroelectric properties of Bi4Zr0.5Ti2.5O12 thin films on LaNiO3 bottom electrode by the sol–gel method

We have investigated the preparation and properties of Bi4Zr0.5Ti2.5O12 thin films on the LaNiO3 bottom electrode. The Bi4Zr0.5Ti2.5O12 thin films were fabricated on the LaNiO3 bottom electrode using the sol–gel method. The structure and morphology of the films were characterized using x-ray diffraction and scanning electron microscopy. The results show that the films are a perovskite phase with a dense microstructure. The 2Pr and 2Vc of the Pt/BZT/LaNiO3 capacitor are 28.2 µC cm−2 and 14.7 V respectively under the applied voltage of 25 V. After the switching of 1 × 1010 cycles, the Pr value decreases to 87% of its pre-fatigue values. The dielectric constant and the dielectric loss are about 204 and 0.024 at 1 kHz, respectively. The films show good insulating behaviour according to the test of leakage current.

Fabrication and characteristics of Au/PZT/BIT/p-Si ferroelectric memory diode

Abstract A ferroelectric memory diode that consisted of Au/PZT/BIT/p-Si multilayer configuration was fabricated. The Pb(Zr 0.52 Ti 0.48 )O 3 (PZT) ferroelectric films with a c -axis oriented Bi 4 Ti 3 O 12 (BIT) buffer layer were deposited on a p-Si(1xa00xa00) substrate by pulsed laser deposition technique. The ferroelectric characteristics and the electrical characteristics were measured respectively. The results suggested that the growth of the BIT ferroelectric layer was helpful to increase the memory window and to reduce the current density by impairing the serious interaction and interdiffusion at the ferroelectric/Si interface. The C–V hysteresis loop showed a memory effect due to the ferroelectric polarization of PZT/BIT films. The I–V curve was Schottky-diode-like and had a hysteresis loop due to the ferroelectric remanent polarization. We confirmed our diode had nonvolatile and nondestructive memory readout operation. After applied a writing voltage of +5 V for logic “1” and −5 V for logic “0” respectively, the reading currents were 0.1 and 0.05 μA at a reading voltage of +2 V correspondingly.

Characteristics of Pb(Zr0.52Ti0.48)O3 Thin Films on p-Si with a Buffer Layer of Bi4Ti3O12 Prepared by Pulsed Laser Deposition

The Pb(Zr0.52Ti0.48)O3 ferroelectric films with a c-axis oriented Bi4Ti3O12 buffer layer were deposited on p-Si(100) substrate by pulsed laser deposition (PLD) technique. The Pb(Zr0.52Ti0.48)O3 films were found to grow with a preferred orientation along (110) direction. Good ferroelectric properties were obtained for a 400 nm thick Pb(Zr0.52Ti0.48)O3/Bi4Ti3O12 film system with Au electrodes: Pr and Ec were 20 µC/cm2 and 48 kV/cm respectively. The memory window of capacitance–voltage (C–V) charactristics enlarged obviously and the current density reduced nearly two orders of magnitude after introducing the BIT buffer layer. The decay in remnant polarization was only 10% up to at least 109 bipolar switching cycles.

Hysteresis loops of first-order ferroelectric bilayers or superlattices and their size effect

Based on Landau–Ginzburg phenomenological theory, a first-order ferroelectric bilayer or superlattice with an antiferroelectric interface coupling has been studied by taking into account the spatial variation of polarization within each constituent film and the surface effect. The hysteresis loops are obtained and the size effect of a bilayer is discussed. The loop patterns vary between typically antiferroelectric and typically ferroelectric depending on the thickness ratio, the coupling constant, the thickness and the extrapolation length. The antiferroelectric coupling has a great effect on the phase transition of a bilayer. It is shown that the size-driven phase transition cannot be observed in a ferroelectric bilayer in the case of strong antiferroelectric coupling.

EFFECT OF ANNEALING TEMPERATURE ON LEAKAGE CURRENT CHARACTERISTICS OF Bi3.25La0.75Ti3O12 THIN FILMS PREPARED BY SOL-GEL METHOD

ABSTRACT Bi3.25La0.75Ti3O12 films are prepared on Pt/Ti/SiO2/Si substrate by Sol-Gel method. The XRD patterns indicate that the BLT films annealed at different temperatures are randomly orientated and the single perovskite phase is obtained at 550°C annealed. The ferroelectric properties and leakage current characteristics are studied. The remnant polarization increases and the coercive field decreases with the annealing temperature increasing. The leakage current density of the BLT films annealed at 700°C is about 5.8 × 10−8 A/cm2 at 250 kV/cm. There are unambiguously differentiated mechanisms responsible for electrical transport at different electric field regimes in the BLT films.

EFFECT OF EXCESS Pb IN PT LAYERS ON MICROSTRUCTURE AND DIELECTRIC CHARACTERISTIC OF PT/PZT/PT THIN FILMS

ABSTRACT The Pb1 + xTiO3/PbZr0.3Ti0.7O3/Pb1 + xTiO3(PT/PZT/PT) sandwich structure thin films with different excess Pb content (x = 0, 0.05, 0.10, 0.15, 0.20) in PT precursor were prepared by sol-gel method. The XRD results show that the crystalline behave of PT/PZT/PT films is quite different to the PZT films, it is greatly affected by temperature and excess Pb content (x) in PT layers. The excess Pb content (x) in PT layers effects the crystallization of the formation of perovskite-phase of PZT layers through the effect of perovskite-phase formation of the PT layers. The SEM results showed that the dense and uniform of grain size surface morphology of PT/PZT/PT thin films annealed at 650°C appeared when the excess Pb cintent x = 0.05, 0.10 and 0.15. The results of ferroelectric, dielectric constant and dielectric loss characteristic of the films correlated obviously to the crystalline behaviors and excess Pb content(x) in PT layers. A higher remnant polarization and better dielectric constant and dielectric loss characteristic were obtained for the films of excess Pb content x = 0.10 and 0.15 in PT layers.

A COMPACT MODEL FOR THE SIMULATION OF FERROELECTRIC CAPACITOR

ABSTRACT A compact model for description of the ferroelectric hysteresis loop behavior based on the dipole switching theory was derived. A cell of ferroelectric crystal is just as an equivalent dipole, so the hysteresis loop characteristic of ferroelecticity is the polarization characteristic of dipole in the electric field. The simulation results show good agreement with the experiment data for various hystersis loops. Therefore the model can be used for both circuit simulation and provide better intuition into the ferroelectric material behavior.

Fabrication and Characterization of Metal/Ferroelectric/Semiconductor Field Effect Transistor with the Ag/Bi4Ti3O12/p-Si(100) Structure

Metal-ferroelectric-semiconductor field-effect-transistors (MFS-FETs) with the Ag/Bi4Ti3O12/p-Si (100) structures were fabricated. The I-ds-V-g hysteresis curve of the FET shows the counter-clockwise direction, which demonstrates the charge of channel conductivity due to the ferroelectric polarization of Bi4Ti3O12 and the memory window with a gate voltage of +/-6V was 1.2 V. The current ratio of I-ds(on) to I-ds(off) was over two orders in magnitude at zero gate voltage which indicates the MFS-FET can be used in nondestructive readout (NDRO) applications.

Micro-Conductivity Rapid Detection Research of Electrophoresis Chip Based on Orthogonal Vector Lock-In Amplifier on FPGA

A capacitively coupled contactless conductivity detection (CD) method of capillary electrophoresis microchip based on orthogonal vector lock-in amplifier on FPGA is presented. The digital orthogonal vector lock-in amplifier is configured by assembling LPM_MULT、ALTMULT_ADD、 Low-pass Filter and other IP core. The orthogonal driving signals are generated by custom DDS IP core based on DSP Builder software, the embedded CPU, NIOS II, achieves the flexible control of detection system. The simulation results show that it can effectively weaken noise interference. Simultaneously, it can provide a novel design method for the miniaturization, integration and control of biochip system. Keywords-SOPC; orthogonal vector lock-in amplifier; electrophoresis chip; C4D; DDS.