Jung Han Kang

Analysis of Bias Stress Instability in Amorphous InGaZnO Thin-Film Transistors

In this paper, we report an analysis of electrical bias stress instability in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Understanding the variations of TFT characteristics under an electrical bias stress is important for commercial goals. In this experiment, the positive gate bias is initially applied to the tested a-IGZO TFTs, and subsequently, the negative gate bias is applied to the TFTs. For comparison with the subsequently negative-gate-bias-applied TFTs, another experiment is performed by directly applying the negative gate bias to the tested TFTs. For the positive gate bias stress, a positive shift in the threshold voltage (Vth) with no apparent change in the subthreshold swing (SSUB) is observed. On the other hand, when the negative gate bias is subsequently applied, the TFTs exhibit higher mobility with no significant change in SSUB, whereas the shift of the Vth is much smaller than that in the positive gate bias stress case. These phenomena are most likely induced by positively charged donor-like subgap density of states and the detrapping of trapped interface charge during the positive gate bias stress. The proposed mechanism was verified by device simulation. Thus, the proposed model can explain the instability for both positive and negative bias stresses in a-IGZO TFTs.

Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (VGS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all VGS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (DVth )a s a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the DVth is generated by carrier trapping but not defect creation. It is also observed that the DVth shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (NT) and free carriers resulted in the increase of DVth as the channel layer thickness increases. 2011 Elsevier Ltd. All rights reserved.

Mobility enhancement in amorphous InGaZnO thin-film transistors by Ar plasma treatment

The effects of Ar plasma treatment on the back-channel of amorphous InGaZnO (a-IGZO) thin-film transistors are investigated. A decrease in metallic ion-oxygen bonding in the Ar plasma-treated a-IGZO channel layer was observed by X-ray photoelectron spectroscopy (XPS) depth profile analysis. An increase in the channel charge carrier concentration is estimated from the increased oxygen vacancy atomic ratio using XPS curve decomposition analysis. The plasma-treated area of the a-IGZO back-channel is varied with a photoresist screening layer with a varied open window length (Lp). From the Lp-dependent channel resistance analysis, a carrier concentration-dependent field-effect mobility enhancement is observed.The effects of Ar plasma treatment on the back-channel of amorphous InGaZnO (a-IGZO) thin-film transistors are investigated. A decrease in metallic ion-oxygen bonding in the Ar plasma-treated a-IGZO channel layer was observed by X-ray photoelectron spectroscopy (XPS) depth profile analysis. An increase in the channel charge carrier concentration is estimated from the increased oxygen vacancy atomic ratio using XPS curve decomposition analysis. The plasma-treated area of the a-IGZO back-channel is varied with a photoresist screening layer with a varied open window length (Lp). From the Lp-dependent channel resistance analysis, a carrier concentration-dependent field-effect mobility enhancement is observed.

One-Dimensional Semiconductor Nanostructure Based Thin-Film Partial Composite Formed by Transfer Implantation for High-Performance Flexible and Printable Electronics at Low Temperature

Having high bending stability and effective gate coupling, the one-dimensional semiconductor nanostructures (ODSNs)-based thin-film partial composite was demonstrated, and its feasibility was confirmed through fabricating the Si NW thin-film partial composite on the poly(4-vinylphenol) (PVP) layer, obtaining uniform and high-performance flexible field-effect transistors (FETs). With the thin-film partial composite optimized by controlling the key steps consisting of the two-dimensional random dispersion on the hydrophilic substrate of ODSNs and the pressure-induced transfer implantation of them into the uncured thin dielectric polymer layer, the multinanowire (NW) FET devices were simply fabricated. As the NW density increases, the on-current of NW FETs increases linearly, implying that uniform NW distribution can be obtained with random directions over the entire region of the substrate despite the simplicity of the drop-casting method. The implantation of NWs by mechanical transfer printing onto the PVP layer enhanced the gate coupling and bending stability. As a result, the enhancements of the field-effect mobility and subthreshold swing and the stable device operation up to a 2.5 mm radius bending situation were achieved without an additional top passivation.

Conduction instability of amorphous InGaZnO thin-film transistors under constant drain current stress

Conduction characteristics of amorphous InGaZnO thin-film transistors were investigated by applying constant drain current with gate bias (VGS) modulation. Constant drain current in the off-current (Ioff) level from the transfer characteristic was applied to the drain electrode and the measured drain voltage with the gate bias sweep. The normalized channel conductance (Gd) characteristics were extracted from transfer characteristics and the gate bias modulated drain voltage characteristics with constant drain current stress were compared with the characteristics. The drain voltage induced by the constant drain current stress showed simultaneous transition from off-state with generation current dominant region with increasing drain bias (VDS) to the turn-on state. The high electric field at the drain electrode edge was

Variability modeling of RF characteristics for multi-finger MOSFETs using statistical methods

In this paper, the AC circuit model of multi-finger MOSFET for RF application is investigated. Test structures varying with the gate width and the number of fingers are fabricated in 0.35-μm TSMC process. The s-parameters of test structures are measured from 50MHz to 10GHz. The equivalent circuit model is proposed by hybrids of BSIM3 and the parasitic components. The parasitic components are extracted by optimizing the parameters using the measured DC and RF characteristics. Based on the extracted circuit models, the extracted parameters are verified by the analysis of variance.

Effects of Electrical Characteristics on the Non-Rectangular Gate Structure Variations for the Multifinger MOSFETs

In this paper, modeling methodology of electrical characteristics for non-rectangular gate structured multifinger metal-oxide-semiconductor field-effect transistors based on minimum channel length is proposed. The test structures are fabricated and the parasitic model parameters are extracted using the measured data for the proposed model. The proposed model can support better physical explanation than the previously presented integrated length model. The proposed model can precisely explain the electrical characteristics and is supported by theoretical equations for non-rectangular gates, such as the threshold voltage, the saturation voltage, the saturation current, and the leakage current. However, the previous integrated length model cannot sufficiently explain the electrical characteristics for non-rectangular gates although it is sustained by theoretical equations. Furthermore, this paper shows the relationship between gate poly area and the electrical characteristics. As a result, the electrical characteristics are dependent on the variation of the minimum of the gate length, rather than the profile of gate length variation.

Material characterization and process modeling issues of high-k dielectrics for FET applications

In this paper, characterization and modeling issues of high-k dielectrics are reviewed and investigated. At first, thermal and plasma enhanced atomic layer deposition (T-ALD and PE-ALD) process effects on high-k dielectric thin film characteristics is analyzed and neural network (NNet) process modeling methodology applied to high-k thin film processing is reviewed. Characteristic variations of high-k dielectric layers and process variation effects are then examined. Comparison of electrical characteristic variation and post-metallization annealing (PMA) effects on different high-k dielectric thin film grown by molecular beam epitaxy (MOMBE) process is also presented. Annealing effects in different ambient gas environments on device characteristics are also examined. Finally, the nanowire FET using the ZnO nanowire on HfO2 dielectrics is presented for the next-generation FET applications.

Green's function based 2-D MOSFET modeling for random dopant fluctuation

Random dopant fluctuation (RDF) in MOSFET has been an issue recently due to the scaling down of CMOS process. Impedance field method has mainly used as a solution to predict effects of RDF previously. In addition, a new model, which converts a Poissons equation into a Greens function based form, estimates inhomogeneous term of differential equation through charge distribution. In this paper, a Greens function based 2-D MOSFET model is proposed. The model starts from the Poissons equation to obtain the initial conditions and then sum of Greens function based formula and Laplace equation provide voltage distribution, charge distribution, and drive current as the modeling results. We also verify its effectiveness through the comparison with TCAD simulation results.

Current stress instability analysis of amorphous InGaZnO thin film transistors

1. Introduction Recent researches from the demands of large size liquid crystal flat panel displays, low cost process and higher performance arouse great interest on amorphous oxide semiconductor based thin-film transistors (TFTs) as an alternative of a-Si TFTs. To achieve device reliability and stability under various current/voltage bias, temperature, and light injections, various researches on amorphous InGaZnO (a-IGZO) channel material have been reported [1,2,3]. It is reported that the deterioration of a-IGZO channel is mainly induced by conditions of trap state, such as oxygen vacancy and it can be enhanced by passivation or annealing process [3]. However, researches on current injection to the TFT channel need to be investigated to achieve optimized performance characteristics at current stress condition. In this study, we investigated channel degradation characteristics applying current stress to a-IGZO channel with different bulk thickness.