Junji Michiyama

A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application

A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.

A 45nm single-chip application-and-baseband processor using an intermittent operation technique

Mobile phones demand high-performance application processors to support digital television viewing, 3D games and heavy-load applications. On the other hand, mobile phones also demand low power consumption of the application processors for voice telephony, music player and light-load applications. Consequently, the chip for mobile phones must achieve appropriate power consumption for each application over a wide range of performance. Furthermore, because next generation mobile phones require more functions and higher performance than the current generation, it is important for the chip to both integrate various functions and to shrink the implementation area using the next process technology in order to reduce cost. Single-chip application-and-baseband processors [1, 2] currently exist in the mobile phone market. The chip presented here is a single-chip application-and-baseband processor using 45nm process technology. It introduces an intermittent operation technique to reduce the power consumption for light-load applications. Furthermore, it has 4 power management mechanisms, power-gating, VDD control, VBB control and VSS control.

A 90 mW MPEG4 video codec LSI with the capability for core profile

A single-chip MPEG4 video codec LSI with 20 Mb embedded DRAM performs a QCIF 15 Hz H.263 codec, a Simple at L1 codec, and Core at L1 decoding. It consumes 90 mW at 54 MHz. This chip integrates a programmable DSP, 8 dedicated hardware engines, and interface units on a 75.68 mm/sup 2/ die using 0.18 /spl mu/m 1.8 V quad-metal CMOS technology.