Junji Ohara

A new deep reactive ion etching process by dual sidewall protection layer

This paper describes a new deep reactive ion etching (D-RIE) process which drastically improves the aspect ratio of the etched trench. The conventional D-RIE process obtains the high aspect ratio trench etching with the protection layer, such as a polymeric layer. The etching anisotropy is limited in this process because this protection layer prevents not only lateral etching, but also vertical etching. In contrast, the new process we developed intensively prevents lateral etching with a dual protection layer consists of a polymeric layer and a SiO/sub 2/ layer on the trench sidewall. Therefore the etching anisotropy and the aspect ratio can be improved. Furthermore, this process can only be performed by switching the introducing gas into the etching chamber.

Improvement of Si/SiO/sub 2/ mask etching selectivity in the new D-RIE process

This paper describes an improvement of Si/SiO/sub 2/ mask etching selectivity in the new D-RIE process that we presented in MEMS 2000. This process, which repeats the conventional D-RIE (ASE process) and O/sub 2/ plasma irradiation processes alternately, can improve the aspect ratio due to the prevention of lateral etching. However, the SiO/sub 2/ mask erosion of this process was 2.7 times as high as that of the conventional D-RIE process because the SiO/sub 2/ mask is sputtered by oxygen ion in the O/sub 2/ plasma irradiation process. Therefore the highest aspect ratio:46 was restricted by mask consumption. In this study, we suppressed the SiO/sub 2/ mask consumption. This suppression improves etching selectivity and increases the highest aspect ratio up to 60. Furthermore, the required process time is reduced to 2/3 of the prior result.

Improvement of high aspect ratio Si etching by optimized oxygen plasma irradiation inserted DRIE

This paper describes an advanced Si-deep etching process achieving a high aspect ratio with excellent verticality by the improvement of the O2 plasma source condition in the oxygen plasma irradiation inserted deep reactive ion etching (OP-DRIE) process that we have developed. The conventional DRIE process which we call the Bosch process has a trade-off relation between the high aspect ratio and verticality in the trench profile. Our developed process technique, repeating the conventional DRIE and the O2 plasma irradiation process alternately, can achieve the vertical trench profile with a higher aspect ratio than that of the conventional DRIE process. In order to maximize an advantage of the developed process, a thickness of the SiO2 layer formed by irradiation of O2 plasma should be large enough as a protection layer. However, because of insufficient SiO2 thickness formed by O2 plasma, the aspect ratio has been limited in previous work. Furthermore, mask material (SiO2) erosion which is another limitation factor of the aspect ratio is increased by the insertion of O2 plasma irradiation. In this paper, we have investigated optimum O2 plasma source conditions that allow an increase in SiO2 thickness with a high oxidation rate, and at the same time, with less mask erosion on the top of the wafer. We have clarified the effects of frequency and pulsed/CW modes of the plasma source on the effectiveness in SiO2 formation. From the obtained oxygen plasma source condition, we achieved the etched Si trench having an aspect ratio of over 70 with excellent verticality (uniform trench width).

Improvement of the optical transmittance of a micro prism made from a Si substrate by DRIE, oxidation and SiO2 film refilling

In this paper, we report on an improved fabrication process of micro-optical elements (e.g. lens and prism) with a height of 100 µm monolithically fabricated on a silicon substrate. The previously reported fabrication process is composed of (1) fine-pitched trench etching using DRIE followed by (2) thermal oxidization converting Si trench walls to transparent SiO2. Though 100% of Si walls had been converted to SiO2, it was difficult to completely squeeze out the remaining voids between SiO2 layers. Here, SiO2 deposition by CVD was added to the previous process as the third step to fill up the remaining voids. The first step (i.e. DRIE) was also modified to form trenches with a larger tapered angle at the top region than the other regions. The improved process made it possible to refill the trenches without voids with an only exception at the top region. The transmittance of the optical devices has improved from 67 to 91% by our new process.

A new fabrication process for micro optical elements using drie and oxidation

We have developed a new fabrication process of micro optical elements by applying DRIE (Deep Reactive Ion Etching) process and thermal oxidation, which enables us to make micro lenses and prisms on a silicon substrate without assembling. This process can also form other optical elements, such as light wave-guides by changing mask pattern.

A New Fabrication Method of Ultra-Small Laser Scanning Module

We report for the first time that an ultra-small laser scanning module of millimeter size has been realized. We have demonstrated electronic scanning by switching the current without any moving parts. Having no moving parts enables high reliability, and the system volume can be greatly reduced. This fabrication technology that we employed enables very precise mass production of micro-optical elements such as prisms, lenses and light waveguides, because all fabrication steps are carried out using the same semiconductor process. These micro-optical elements are formed on the substrate simultaneously using single etching mask.

3D system simulation study of power integrity using Si interposer with distribution TSV decoupling capacitors

Improvements of power integrity (PI) on high-speed system have been studied from the point view of many structures in huge papers[1][2][3]. In this study, the PI simulation for the A-D mixed 3D stack chip system by TSV is done in many kinds of power sources. We already studied on the interposer with large area MIM capacitor was effective for the 3D system [4][5], that understood as an area structure made lower input impedance ever GHz region. As a result, we can find which the input impedance is related largely with the DeCap TSV distribution pitch. Consideration of approach wiring to distributed DeCap TSVs is the key issue for the better PI performance as the result.