Junji Sakai

FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals

We propose a secure platform on a chip multiprocessor, FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multigrained separation mechanisms. Four new technologies support the FIDES platform: bus filter logic, XIP kernels, policy separation, and dynamic access control. With these technologies, the FIDES platform can tolerate both application-level and kernel-level bugs on an actual download subsystem. Thus, the best-suited platform to secure next generation mobile terminals is FIDES.

VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals

The authors propose new processor virtualization architecture, VIRTUS, to provide a dedicated domain for pre-installed applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS feature three new technologies: VMM asymmetrization, dynamic inter-domain communication and virtualization-assist logic, and the first in the world to virtualize an ARM-based multiprocessor

Power Saving in Mobile Devices Using Context-Aware Resource Control

We present an effective power reduction scheme for recent mobile devices, e.g., Android devices, which tend to have problems with battery life because some of their applications may be running continuous sensor operations. We propose a context-aware method to determine the minimum set of resources (processor cores and peripherals) that results in meeting a given level of performance. With it, unnecessary processor cores and peripherals can be switched-off without degrading overall performance. Our experimental results indicate that its use can result in a 45% reduction in total power consumption. Since our method does not require applications to be modified, it can even be used easily with downloaded applications.

Processor virtualization for secure mobile terminals

We propose a processor virtualization architecture, VIRTUS, to provide a dedicated domain for preinstalled applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies, namely, VMM asymmetrization, dynamic interdomain communication (IDC), and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor. Evaluations have shown that VMM asymmetrization results in significantly less performance degradation and LOC increase than do other VMMs. Further, dynamic IDC overhead is low enough, and virtualization-assist logic can be implemented in a sufficiently small area.

Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

We propose a method for dynamic security domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security domain in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: 1) self-transition management and 2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security domains. The increase in binary code size is less than 40 KB, and the time required for individual state transitions is of a single-millisecond order. This scaling is the first in the world to make possible dynamic changing of the number of processors within a security domain on an ARM SMP.

Towards scalable and secure execution platform for embedded systems

Reliability of embedded systems can be enhanced by multicore and partitioning approaches. Physical partitioning based on AMP multicore achieves runtime stability of multiple applications in a system and prevents the whole system shutdown as well even when a malicious code creeps in. Combined with logical partitioning by processor visualization and SMP technologies, the multicore architecture could realize more flexible and more scalable platform for future embedded systems.

Dynamic security domain scaling on embedded symmetric multiprocessors

We propose a method for dynamic security-domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security-domain (i.e., dynamically yielding processors to other security-domains) in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: (1) self-transition management and (2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security-domains. The increase in OSs in binary code size is less than 1.5%, and the time required for individual state transitions is on the order of a single millisecond. This scaling is the first in the world to make possible the dynamic changing of the number of processors within a security-domain on an ARM SMP.

A robust seamless communication architecture for next-generation mobile terminals on multi-CPU SoCs

We propose a robust seamless communication architecture that enables legacy mobile terminal software designed for single-CPU processors to be run on multi-CPU processors without any software modifications. This architecture features two new technologies: proxy processes, which help achieve the design of its user-level system-call hooking and a robust design method, which reduces bandwidth variation by systematic parameter optimization. Our evaluations confirmed that this architecture achieves fundamental features with satisfactory performance, that we have succeeded in getting actual mobile terminal software to run on three CPUs without modifying the software, and that the robust design method reduces bandwidth variation by 21%.

Multitasking Parallel Method for High-End Embedded Appliances

Embedded appliances such as high-end cell phones require not only high performance but also a performance guarantee. The authors demonstrate a performance guarantee framework using an asymmetric multiprocessing approach. They implemented the proposed method on a multicore processor using Linux. Evaluation results show that the method improves the performance guarantee while maintaining software compatibility.

Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors

Super Resolution image processing (SR) is a heavy task for a todays mid-range Xeon server. To accelerate SR, we utilize a server system with manycore coprocessor, Intel Xeon Phi coprocessor. Function offload model is a usual execution model for those systems. However it is difficult for SR to increase utilization of both host processors and coprocessors by the model. We propose a virtual pipeline model which can fully utilize both processors. Experimental results show that our SR improves performance 3.3 times and performance/watt 1.5 times. Our SR achieves 30 frames per sec from SD to HD.