Junqing Zhou

The impact of metal hard-mask AIO etch on BEOL electrical performance

In advanced CMOS technology nodes with Cu/low-k interconnect, as Cu line CD continues being scaled, the back-end-of-line (BEOL) electrical performance significantly impacts the chip operation speed by total RC (Resistance and Capacitance) delay. The resistance includes metal sheet resistance (RS) and via contact resistance (RC), while the capacitance includes inter metal and intra metal capacitance. Metal sheet resistance is always coupled with intra metal capacitance, so trench CD and profile dominate both metal resistance and intra metal capacitance if low-k damage is well controlled. The trench CD and profile associated with lower RC delay are proposed. If gap filling capability is considered, tapered trench profile is preferred and then metal HM CD and film thickness need be optimized to meet the RC delay target. The contact resistance of via is dominated by via contact area. Via bottom CD and trench top CD decide the contact area together and both of them are critical for KV RC reduction. Via chamfer profile effect on via resistance is insignificant. Partial via etch depth plays totally different role in KV RC on two different kinds of film stack. The mechanism of this phenomenon is addressed. Such complex correlation between via and trench is investigated in this paper by means of electrical performance testing, meanwhile the impact of AIO etch on BEOL electrical performance is revealed correspondingly.

The Cu exposure effect in AIO etch at advanced CMOS technologies

In advanced CMOS technology nodes with Cu/low-k interconnect, metal hard-mask approach AIO etch is the key process to define the physical structure of Cu line and via. The via hole and via slot always land on lower metal Cu as design rule requested. The time of beneath Cu exposed to fluorocarbon plasma in etch stop layer (ESL) opening step, especially for the via slot area, is critical for final trench depth and residual defect formation. The mechanism and solution of this phenomenon are addressed.

Pulsed capacitively coupled plasmas for AIO etch process

Pulsed capacitively coupled plasmas (CCP) was applied to self-aligned-via (SAV) based all-in-one (AIO) etching process. Effects of bias and synchronous pulsed plasmas on the AIO etching process were analyzed to improve the reliability and reduce the RC delay in back-end-of-line (BEOL) copper interconnect system. For steps of hard-mask open and partial via etch, synchronous pulsed plasmas were applied. Etch front roughness could be reduced using shorter duty cycle, which might be related to its more uniform deposition of polymer and higher power at the initial active-glow period. For steps of trench and liner removal etch, bias pulsed plasmas were applied. The chamfer profile of via could be improved, and larger bottom critical dimension (BCD) of via could be achieved with shorter duty cycle, which might be related to its higher selectivity between N-doped carbon (NDC, SiCN) and low-k (SiCOH).

Study of BEoL dual damascene ULK etch and the correlation to Cu gapfill performance

As logic technology keeps shrinking to 28nm and below, Ultra Low-k (ULK) dielectric film is widely used in BEoL (Back End of Line) to improve RC performance. To reduce k value damage, weaker post dry-etch cleaning is used to avoid methyl group loss, but the etch by-product removal capability is reduced also. Even with softer cleaning, the trench and via profile still will be affected due to ULK film is more sensitive to wet cleaning compared to low-k and TEOS film. The residual polymer and the sidewall profile will limit the subsequent Cu gap filling process margin, which needs more precise control of etch process. In the this paper, by means of post CMP defect scan, we demonstrate the correlation between Cu void performance and dual damascene profile, etch chemistry combination and loading control. Mechanisms of difference void formations are investigated. Based on that, corresponding tuning methods are investigated.

Metal hard-mask based AIO etch challenges and solutions

Trench-first-metal-hard-mask (TFMHM) approach has been widely utilized for copper interconnect formation since 45nm CMOS technology node. In TFMHM process integration development, four major challenges have to be solved. The first is the gap-fill due to the small top trench CD and the introduction of metal hard mask; the second is to meet the electrical targets through lower capacitance, lower metal sheet resistance and lower via contact resistance; the third is to meet yield requirement that ensure no short, bridge and open in all the design rule allowed patterns, and eliminate all killer defects; the last is the reliability related issues including metal and via related TDDB, upstream EM and downstream EM. Coupled with the optimization of wet clean process and proper choice of metal hard mask, a smooth and tapered trench profile could be delivered and the gap-fill performance could be greatly improved. The optimization of barrier/seed process coupled with the desired trench profile, via bottom CD and via chamfer profile, the on-target electrical performance could be achieved. The via bottom CD and chamfer profile are also critical to interconnects and etch process parameter optimization is important for defect elimination. With partial SAV process optimization, via related TDDB issue is solved and trench related TDDB is also not a problem for the above gap-fill friendly trench profile. For EM, we found the downstream EM lifetime is improved by gap filling friendly process and proper copper line CD.