Junyi Du

Bit Mapping Design for LDPC Coded BICM Schemes With Multi-Edge Type EXIT Chart

In this letter, we consider the bit mapping (BM) design for regular low-density parity-check (LDPC) coded bit-interleaved coded modulation (BICM) schemes. We propose a check-node type distribution and develop multi-edge type extrinsic information transfer (EXIT) functions for the regular LDPC coded BICM schemes. Based on the EXIT functions, we propose a two-phase design method to generate the optimized practical BM in terms of the lowest decoding threshold for a given finite length LDPC code. Simulation results show that the proposed BM has a better decoding threshold compared with those of the existing works.

The multi-step PEG and ACE constrained PEG algorithms can design the LDPC codes with better cycle-connectivity

This paper proposes two new cycle-optimized algorithms, called the multi-step progressive edge-growth (PEG) algorithm and the multi-step approximate cycle extrinsic message degree (ACE) constrained PEG algorithm, to design an LDPC code with larger girth and better cycle-connectivity. In addition, an efficient method is developed to calculate the distances between the variable nodes (VNs) and the check nodes (CNs) in the proposed algorithms. Simulation results show that compared to the conventional cycle-optimized algorithms, the proposed algorithms can achieve both better cycle-connectivity and foreseeable lower error floors.

The Joint Demodulation and Decoding for BICM-ID System with BEC Approximation and Optimized Bit Mapping

To improve the performance further for the bit- interleaved coded modulation with iterative decoding (BICM-ID) system, a modified extrinsic information transfer (EXIT) model is presented, in which the decoding and the demodulation are modeled as two iterative processing units. By using the binary erasure channel (BEC) approximation for the a priori AWGN channel, the analytical formulation of mutual information for sub-channels in M-QAM are obtained. Besides, the grid depth-first searching algorithm (GDFSA) is modified for designing the optimal bit mapping distribution with minimum convergence rate. Using the DVB-S2 rate-0.5 64800-bit low-density parity-check (LDPC) code as demonstration, the simulations show that the BER performances achieve 0.225/0.650dB gains at 10^-5 for 16-QAM/32-QAM under AWGN channel, compared to the consecutive bit mapping.

A progressive edge growth algorithm for bit mapping design of LDPC coded BICM schemes

In this paper, we consider the design of the bit mapping in low-density parity-check (LDPC) coded bit-interleaved coded modulation (BICM) schemes. We introduce a two-layer bipartite graph to represent the LDPC coded BICM scheme where a new bit mapping graph linking sub-channels to variable nodes (VNs) is added to the conventional Tanner graph. We propose a progressive edge growth (PEG) algorithm to design the bit mapping for the BICM scheme. The design paradigm is to provide more protections to the VNs that are allocated to the sub-channels with the lowest mutual information. We define a novel concept of unreliable depth profile to classify the reliability of the VNs. By connecting more reliable edges to the least reliable VNs, we can significantly improve the reliable edge distribution for the unreliable VNs, thus improve the extrinsic information in the iterative decoding. The proposed bit mapping algorithm is employed for the design of the LDPC coded BICM with 64-QAM and 256-QAM. Simulation results show that the proposed design can considerably improve the error performance, compared to the conventional consecutive bit mapping strategy.

A New Multi-Edge Metric-Constrained PEG Algorithm for Designing Binary LDPC Code With Improved Cycle-Structure

The progressive edge-growth (PEG) algorithm constructs an edge in each stage to maximize the variable node (VN) of interest’s local girth in real time. Thus, this VN’s local girths, after more than one edge is added to the current tanner graph (TG) setting, may not be maximized relative to that TG setting. To address this problem, we define the multi-edge local girth and edge-trial, and based on these definitions, propose a new multi-edge metric-constrained PEG algorithm (MM-PEGA) to improve the design at each VN. The MM-PEGA constructs an edge in each stage that, relative to the current TG setting, can potentially maximize the VN of interest’s local girth after a certain number (up to the edge-trial) of edges are added to the TG setting. We first analyze the properties of the multi-edge local girth, and then propose an algorithm for calculating the multi-edge local girth. We also propose a method for accelerating the MM-PEGA. Moreover, we generalize the MM-PEGA for improving different PEG-like designs. According to the theoretical analysis, increasing the edge-trial of the MM-PEGA is expected to positively affect the cycle-structure and the error performance of resulting low-density parity-check (LDPC) code. This expectation is verified by simulations.

An algebraic approach to design low rate low density parity check code

In this paper, we propose an algebraic approach to design extremely low rate low-density parity-check (LDPC) codes by employing the primitive polynomials. We first investigate the requirements for the polynomials to construct 4-cycle free LDPC codes and then propose an algebraic approach to design the parity check matrix. To achieve a better decoding performance in the extremely low rate region, we propose an extension method to construct more check nodes and virtual variable nodes to obtain more constraints. Our designed LDPC codes have simple encoding and simple decoding features. Simulation results show that our proposed rate-0.03 LDPC code can achieve 2.2 dB gain, compared to the LDPC code designed by the progressive edge growth algorithm with the optimized edge degree distributions described in [7].

Bit Mapping Design for LDPC Coded BICM Schemes with Binary Physical-Layer Network Coding

We propose a new low-density parity-check (LDPC) coded binary physical-layer network coding (PNC) scheme for Gaussian two-way relay channels. In this scheme, we introduce a bit mapper between the LDPC encoder and the modulator, which considers the unequal error protections brought by the high order PSK modulations. We add a new bipartite sub-channel graph consisting of sub-channels and variable nodes (VNs) to the Tanner graph and propose a progressive edge growth (PEG) algorithm to design the bit mapper. The design paradigm is to search for the bit mapping distribution with the lowest decoding threshold by using the extrinsic information transfer (EXIT) chart, and then establish the edges progressively between VNs and sub-channels according to the distribution. The proposed PEG algorithm is employed to design the bit mappers of the schemes with 8-PSK, 16-PSK, 64-PSK and 256-PSK. Simulation results show that the proposed schemes can considerably improve the bit error performance of the PNC XOR messages, compared to the schemes without bit mappers.