Jürgen Biela

Core Losses Under the DC Bias Condition Based on Steinmetz Parameters

The calculation of core losses in inductive components is difficult and has not yet been entirely solved. In particular, it is impossible to predict the influence of a dc premagnetization on the losses without extensive measurements. For this paper, different materials have been tested to gain information on how core losses are influenced by a premagnetization. Measurements on molypermalloy powder, silicon steel, nanocrystalline material and ferrite cores have been performed. The Steinmetz premagnetization graph (SPG) that shows the dependency of the Steinmetz parameters ( , and ) on premagnetization is introduced. This permits the calculation of core losses under dc bias conditions. Such graphs are given for different materials and different operating temperatures. In addition, a detailed description of the test system is given, as high accuracy is crucial.

Improved Core-Loss Calculation for Magnetic Components Employed in Power Electronic Systems

In modern power electronic systems, voltages across inductors or transformers generally show rectangular shapes, including periods of zero voltage. In the stage of zero applied voltage (constant flux), core losses are not necessarily zero. At the beginning of a period of constant flux, losses still occur in the material. This is due to relaxation processes. A physical explanation about magnetic relaxation is given and a new core-loss modeling approach that takes relaxation effects into consideration is introduced. The new loss model is called improved-improved generalized Steinmetz equation and it has been verified experimentally.

SiC power semiconductors in HEVs: Influence of junction temperature on power density, chip utilization and efficiency

With SiC, junction temperatures of power semiconductors of more than 700?C are theoretically possible due to the low intrinsic charge carrier concentration of SiC. Hence, a lot of research on package configurations for power semiconductor operation above 175?C is currently carried out, especially within the automotive industry due to the possible high ambient temperatures occurring in hybrid electric vehicles (HEVs). This paper shows, that a higher junction temperature though does not necessarily guarantee a higher utilization of the SiC chips with respect to the current that the device can conduct without overheating. The reason is, that for most power devices the power losses start to increase very rapidly at high junction temperatures while the power that can be dissipated always increases linearly with the junction temperature. The junction temperature, where the device current starts to decrease at, is derived for different SiC chips using measured onstate conduction and switching losses in this paper. This paper furthermore analyzes in detail, how the junction temperature on the one hand is influenced by boundary conditions and on the other hand influences itself the core parameters of a converter such as efficiency, the required chip area (i. e. cost) as well as the volumetric power density and thus forms an additional degree of freedom in the design of a power electronic converter. While calculating the optimum junction temperature and analyzing its impact on the system performance, it is demonstrated, how these results can help to find the best suited power semiconductor device for the particular application. The performance of the calculations is shown on a design applied to a drive inverter for hybrid electric vehicles with normally-off SiC JFETs. Operated close to the optimum junction temperature of the SiC JFETs, it reaches a power density of 51 kW/l for the power modules and the air-cooling system, which is shown to be doubled by increasing chip size and using an advanced power semiconductor package with a lower thermal resistance from junction to ambient than the for this case assumed 1 K/W.

Novel AC-Coupled Gate Driver for Ultrafast Switching of Normally Off SiC JFETs

Over the last years, more and more SiC power semiconductor switches have become available in order to prove their superior behavior. A very promising device is the 1200 V 30 A JFET manufactured by SemiSouth. It features a very low on-resistance per die area (2.8 mΩ-cm2), switching within 20 ns, normally off characteristic, high-temperature operation and has already been commercialized in contrast to many other SiC switches. To fully exploit the potential of the SiC normally off JFET, conventional gate drivers for unipolar devices must be adapted to this device due to its special requirements. During on-state, the gate voltage must not exceed 3 V, while a current of around 300 mA (depending on the desired on-resistance) must be fed into the gate; during switching operation, the transient gate-source voltage should be around ±15 V and the low threshold voltage of less than 0.7 V requires a high noise immunity which is a severe challenge as the device has a comparably low gate-source but high gate-drain capacitance. To meet these requirements, several concepts have been published recently. They deal with the challenges mentioned, but they still show certain limitations (e.g., frequency and duty cycle limitations or need for additional cooling due to high gate driver losses). In this paper, a novel gate driver consisting of only one standard gate driver IC, resistors, capacitors, and diodes is designed and experimentally validated. It supplies enough gate current for minimum on-resistance, allows fast switching operation, features a high noise immunity, and can be used for any duty cycle and typical switching frequencies without significant self-heating.

Novel Concepts for Integrating the Electric Drive and Auxiliary DC–DC Converter for Hybrid Vehicles

Cost, volume, and weight are three major driving forces in the automotive area. This is also true for hybrid electric vehicles, which are attracting more and more attention due to increasing fuel costs and air pollution. In hybrid vehicles, the energy distribution system causes a significant share of the volume and the costs. One part of this system is the DC-DC converter that transfers power between the low- and high-voltage buses. In order to reduce the costs and the volume of this converter, this paper presents a new concept for integrating the DC-DC converter functionality into the traction drive system. By using the inverter and the machine to implement a primary bridge leg of an isolated full-bridge DC-DC converter, the total system costs and weight can be reduced. This concept is verified by simulations and experimental results for a scaled prototype. An analytical model of the system has been developed and agrees very well with the measurements. By scaling this model to the power levels typical for hybrid vehicles, it is expected that the efficiency for the DC-DC converter will be greater than 85% for a conventional modulation scheme and above 91% for an optimized switching scheme.

Novel AC coupled gate driver for ultra fast switching of normally-off SiC JFETs

Over the last years, more and more SiC power semiconductor switches became available in low production volumes in order to prove their superior behavior with respect to fast switching speed, low on-resistance per chip area, high voltage range and high temperature operation. A very promising device among those introduced in numerous publications over the last years is the 1200 V 30 A JFET introduced by SemiSouth. It features a very low on-resistance (2.8m Ω cm2), switching operation within 20 ns, a normally-off characteristic and has already been commercialized in contrast to many other SiC switches. To fully exploit the potential of the SiC normally-off JFET, conventional gate drivers for unipolar devices must be adapted to this device due to its special requirements: During on-state the gate voltage must not exceed 3 V, while a current of around 300 mA must be fed into the gate, during switching operation the transient gate voltage should be around ±15 V and the low threshold voltage of 0.7 V requires a high noise immunity which is a severe challenge as the device has a comparably low gate-source but high gate-drain capacitance. To meet these requirements, several concepts have been published recently. They deal with the challenges mentioned, but they also note certain limitations (e. g. frequency and duty cycle limitations or need for additional cooling). In this paper, a novel gate driver consisting only of one standard gate driver IC, resistors, capacitors and diodes is designed and experimentally validated. It supplies enough gate current for minimum on-resistance, allows fast switching operation, features a high noise immunity and can be used for any duty cycle and usual switching frequencies without significant self-heating.

Optimal Design of a 3.5-kV/11-kW DC–DC Converter for Charging Capacitor Banks of Power Modulators

For the generation of short high-power pulses in many applications, power modulators based on capacitor discharge are used, where the peak power is drawn from the input capacitor bank. In order to continuously recharge the energy buffer during operation at a lower average power, usually, power supplies connected to the mains are used. Due to the worldwide variation in mains voltages and the desired ability to adapt the capacitor voltage of the modulator, the power supply has to support a wide input and output voltage range, whereby the supply should draw a sinusoidal current from the mains due to EMI regulations. Additionally, depending on the modulator concept, a galvanic isolation also has to be provided. In order to achieve the mentioned specifications for the considered power supply, a combination of an ac-dc and a dc-dc converter is proposed, whereas the mains voltage is rectified by a three-phase buck-boost converter to 400 Vdc, and thereafter, an isolated dc-dc converter charges the input capacitor bank of the power modulator up to 3.5 kV. This paper focuses on the basic operation and the design of the 3.5-kV/11-kW isolated dc-dc converter, which includes transformer design, efficiency-volume optimization, and component selection. In this paper, compared with the well-known flyback converter, the proposed full-bridge-based topology results in a much higher efficiency and power density.

SiC vs. Si - Evaluation of Potentials for Performance Improvement of Power Electronics Converter Systems by SiC Power Semiconductors

Switching devices based on wide band gap materials as SiC oer a signicant perfor- mance improvement on the switch level compared to Si devices. A well known example are SiC diodes employed e.g. in PFC converters. In this paper, the impact on the system level perfor- mance, i.e. eciency/power density, of a PFC and of a DC-DC converter resulting with the new SiC devices is evaluated based on analytical optimisation procedures and prototype systems. There, normally-on JFETs by SiCED and normally-off JFETs by SemiSouth are considered.

Optimal design of resonant converter for Electrostatic Precipitators

This work presents a design optimization procedure for Series Parallel Resonant Converters (LCC) employed in Electrostatic Precipitator (ESP) power supplies. The system parameters, such as resonant tank elements, are selected in order to reduce semiconductor losses when a typical ESP energization operation range is considered. Here, the sum of the power losses of the switches are predicted for a set of parameters by mathematical models of the LCC resonant converter, and also by loss characteristics of suitable commercially available IGBTs obtained from experimental analysis and datasheet values. The analysis comprises two different control strategies: the conventional Variable Frequency (VF) control and the Dual Control (DC). Finally, the circuit operation and design are verified with a 60kW charging capability LCC resonant converter test set-up. Both control strategies are analyzed by comparing semiconductors losses for five commercial modules.

Design and optimization of medium frequency, medium voltage transformers

Medium voltage, medium frequency transformers (MFTs) are much smaller in size and weight compared to conventional low frequency transformers. The MFTs are very attractive for applications where full control of the power flow and high power density are required, such as power electronic interface in smart grids and traction converter system. With reduced size, the optimal design of MFTs becomes more challenging due to the high isolation requirement and thermal stress. This paper presents a design and optimization methodology for MFTs with emphasis on thermal and insulation design. The improved thermal model for multi-layer windings consisting of litz-wire and the analytical calculation of maximum electric field in core window area are included in the optimization process. By using the methodology, the optimal designs of a 25kW/4 kHz MFT with two commonly used core materials are compared. The possibility of volume reduction by increasing the operating frequency is also investigated.