Justin J. Song

Prediction of CPU idle-busy activity pattern

Real-world workloads rarely saturate multi-core processor. CPU C-states can be used to reduce power consumption during processor idle time. The key unsolved problem is: when and how to use which C-state. We propose a machine learning prediction method and usage model. We evaluate this model with idle traces collected on dual-core and quad-core processor, and find this method can well predict CPUpsilas activity pattern at the error level not exceeding 4%. Compared with existing OS C-state policy, it results in 12% additional CPU power saving and 2% performance improvement. In industry, 12% power saving for any processor is very significant improvement. SPECWeb (which we used consists of 3 different benchmarks - We consistently see doubledigit power saving) is representative ldquofront-endrdquo server workload - it takes >60% DP server market segment share.

Inter-socket victim cacheing for platform power reduction

On a multi-socket architecture with load below peak, as is often the case in a server installation, it is common to consolidate load onto fewer sockets to save processor power. However, this can increase main memory power consumption due to the decreased total cache space. This paper describes inter-socket victim cacheing, a technique that enables such a system to do both load consolidation and cache aggregation at the same time. It uses the last level cache of an idle processor in a connected socket as a victim cache, holding evicted data from the active processor. This enables expensive main memory accesses to be replaced by cheaper cache hits. This work examines both static and dynamic victim cache management policies. Energy savings is as high as 32.5%, and averages 5.8%.