Jyothi Velamala

Circuit aging prediction for low-power operation

Low-power circuit operations, such as dynamic voltage scaling and the sleep mode, pose a unique challenge to aging prediction. Traditional aging models assume constant voltage and averaged activity factor, ignoring the impact of the long sleep period, and thus, result in a significant overestimation of the degradation rate. To accurately predict the aging effect in low-power design, this work first examines critical model assumptions in the reaction-diffusion process that is responsible for the NBTI effect. By using the correct diffusion profile, it then proposes a new aging model that effectively analyzes the degradation under various low-power operations. The new model well predicts the aging behavior of scaled CMOS measurement data (45nm and 65nm) with different operation patterns, especially sleep mode operation and dynamic voltage scaling. Compared to previous aging models, the new result captures the essential role of the long recovery phase in circuit aging, reducing unnecessary guardbanding in reliability protection.

Physics matters: statistical aging prediction under trapping/detrapping

Randomness in Negative Bias Temperature Instability (NBTI) process poses a dramatic challenge on reliability prediction of digital circuits. Accurate statistical aging prediction is essential in order to develop robust guard banding and protection strategies during the design stage. Variations in device level and supply voltage due to Dynamic Voltage Scaling (DVS) need to be considered in aging analysis. The statistical device data collected from 65nm test chip shows that degradation behavior derived from trapping/detrapping mechanism is accurate under statistical variations compared to conventional Reaction Diffusion (RD) theory. The unique features of this work include (1) Aging model development as a function of technology parameters based on trapping/detrapping theory (2) Reliability prediction under device variations and DVS with solid validation with using 65nm statistical silicon data (3) Asymmetric aged timing analysis under NBTI and comprehensive evaluation of our framework in ISCAS89 sequential circuits. Further, we show that RD based NBTI model significantly overestimates the degradation and TD model correctly captures aging variability. These results provide design insights under statistical NBTI aging and enhance the prediction efficiency.

Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction

The aging process due to Negative Bias Temperature Instability (NBTI) exhibits a significant amount of variability and thus poses a dramatic challenge for long-term reliability prediction from short-term stress measurement. To develop a robust prediction method in this circumstance, this work first collects statistical device data from a 65nm test chip with a resolution of 0.2mV in threshold voltage (Vth) measurement. By comparing model prediction from short-term stress data (<;20k second) with direct long-term measurement (up to 200k second), we conclude that (1) the degradation follows a logarithmic dependence on time, as opposed to the conventional power law; (2) the Reaction-Diffusion (R-D) based tn model significantly overestimates the aging rate and exaggerates its variance; (3) the log(t) model, derived from the trapping/de-trapping (T-D) mechanism, correctly captures the aging variability due to the randomness in number of available traps, and accurately predicts the mean and the variance of Vth shift. These results guide the development of a new aging model for robust long-term lifetime prediction.

Compact Modeling of Statistical BTI Under Trapping/Detrapping

The aging process due to negative bias temperature instability (NBTI) is a key limiting factor of circuit lifetimes in CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and dynamic voltage scaling (DVS) in real circuit operation. To overcome these barriers, this paper: 1) practically explains the aging statistics due to randomness in number of traps with the log(t) model, accurately predicting the mean and variance shift; 2) proposes cycle-to-cycle model (from the first principles of trapping) to handle aging under multiple supply voltages, predicting the nonmonotonic behavior under DVS; 3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles; and 4) comprehensively validates the new set of aging models with 65-nm statistical silicon data. Compared with previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard banding during the design stage.

Cross-Layer Modeling and Simulation of Circuit Reliability

Integrated circuit design in the late CMOS era is challenged by the ever-increasing variability and reliability issues. The situation is further compounded by real-time uncertainties in workload and ambient conditions, which dynamically influence the degradation rate. To improve design predictability and guarantee system lifetime, accurate modeling, and simulation tools for reliability are essential to both digital and analog circuits. This paper presents cross-layer solutions for emerging reliability threats, including: 1) device-level modeling of reliability mechanisms, such as transistor aging and its statistical behavior; 2) circuit-level long-term aging models that capture unique operation patterns in digital and analog design, and directly predict the degradation; and 3) simulation methods for very-large-scale designs. Built on the long-term model, the new methods significantly enhance the accuracy and efficiency of reliability analysis. As validated by silicon data, these solutions close the gap between the underlying reliability physics and circuit/system design for resilience.

Optimized self-tuning for circuit aging

We present a framework and control policies for optimizing dynamic control of various self-tuning parameters over lifetime in the presence of circuit aging. Our framework introduces dynamic cooling as one of the self-tuning parameters, in addition to supply voltage and clock frequency. Our optimized self-tuning satisfies performance constraints at all times and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. Our framework features three control policies: 1. Progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2. Progressive-on-state-aging (POSA), which estimates aging by tracking active/sleep mode, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; 3. Progressive-real-time-aging-assisted (PRTA), which estimates the actual amount of aging and initiates optimized control action. Simulation results on benchmark circuits, using aging models validated by 45nm CMOS stress measurements, demonstrate the practicality and effectiveness of our approach. We also analyze design constraints and derive system design guidelines to maximize self-tuning benefits.

Failure diagnosis of asymmetric aging under NBTI

Design for reliability is becoming an important step in the design cycle with CMOS technology scaling, demanding need for efficient and accurate reliability simulation methods in the design stage. Traditional aging analysis does not differentiate NBTI induced delay shift in rising and falling edges, thereby assuming averaging effect due to recovery. It is essential to identify the critical operation conditions that are more susceptible to timing violations under aging. In this paper, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique features of this work include: (1) delay modeling of a digital gate due to threshold voltage (Vth) shift using delay dependence on supply voltage from cell library; (2) asymmetric aging analysis is conducted by recognizing the critical points in circuit operation; and (3) setup and hold timing violations due to NBTI induced path delay shift in logic and clock buffer are investigated. This failure assessment method is further demonstrated in ISCAS89 benchmark circuits using 45nm Nangate standard cell library to extract aging information in critical paths. The proposed failure diagnosis enables resilient design techniques to mitigate circuit aging under NBTI.

Aging Statistics Based on Trapping/Detrapping: Compact Modeling and Silicon Validation

Design for reliability is an increasingly important design step at advanced technology nodes. Aggressive scaling has brought forth reliability issues, such as negative bias temperature instability (NBTI). The aging process due to NBTI exhibits a significant amount of variability for a single device and for multiple devices. As a result, long-term reliability prediction from short-term stress measurement becomes dramatically challenging. With increasing reliability concerns, accurate statistical aging prediction is essential in order to develop robust guard banding and protection strategies during the design stage. To develop an accurate long-term prediction method under variations, this paper first collects statistical device data from a 65-nm test chip with a resolution of 0.2 mV in the threshold voltage Vth measurement. Comparing the aging prediction from short-term stress data (<; 20 k second) with the direct long-term measurement (up to 200 k second), we conclude that: 1) the aging in a pMOS device follows logarithmic time dependence rather than conventional power law; 2) a traditional tn model overestimates the aging rate and the variance for long-term behavior; and 3) a trapping/detrapping (TD)-based log(t) model correctly captures the aging variability due to the randomness in the number of initial available traps, and it accurately predicts the mean and the variance of the Vth shift. These results guide the development of a new aging model for robust long-term lifetime prediction. Furthermore, the effectiveness of the new log(t) model is evaluated by the statistical aging data from 65-nm ring oscillators. Compared with previous models, the new log(t) model based on the TD theory well captures the mean and the variance at the circuit level.

Failure Analysis of Asymmetric Aging Under NBTI

With CMOS technology scaling, design for reliability has become an important step in the design cycle and increased the need for efficient and accurate aging simulation methods during the design stage. NBTI-induced delay shifts in logic paths are asymmetric in nature, as opposed to the averaging effect due to recovery assumed in traditional aging analysis. Timing violations due to aging, in particular, are very sensitive to the standby operation regime of a digital circuit. In this paper, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique contributions of this work include the following: 1) Accurate modeling of aging-induced gate delay shift due to transistor threshold voltage (Vth) shift, using only the delay dependence on supply voltage from cell library, is presented; 2) an efficient simulation flow for asymmetric aging analysis is proposed and conducted at critical points in circuit operation; and 3) timing violations due to NBTI aging are investigated in sequential circuits and the proposed framework is tested in VLSI applications such as DDR memory and SRAM caches. This methodology is comprehensively demonstrated with ISCAS89 benchmark circuits using a 45-nm Nangate standard cell library characterized using predictive technology models. Our proposed failure assessment provides design insights and enables resilient techniques for mitigating digital circuit aging.

Statistical aging under dynamic voltage scaling: A logarithmic model approach

Aging mechanisms, such as Negative Bias Temperature Instability (NBTI), limit the lifetime of CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction in real circuit operation. To overcome these barriers, this work (1) proposes a logarithmic model (log(t)) that is derived from the trapping/de-trapping assumptions; (2) practically explains the aging statistics and the non-monotonic behavior under dynamic voltage scaling (DVS); and (3) comprehensively validates the new model with 65nm silicon data. Compared to previous models, the new result captures the essential role of the recovery phase under DVS, reducing unnecessary guard-banding in reliability protection.