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Dive into the research topics where K B Raja is active.

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Featured researches published by K B Raja.


international conference on computational intelligence and computing research | 2010

Coherent steganography using Segmentation and DCT

K B Shiva Kumar; K B Raja; R. K. Chhotaray; Sabyasachi Pattnaik

The important issue of modern communication is establishing secret communication while using public channel and is achieved by steganography. In this paper, we propose Coherent Steganographic Technique using Segmentation and Discrete Cosine Transform (CSSDCT). The cover image is divided into 8∗8 blocks and DCT is applied on each block. The number of payload MSB bits is embedded into DCT coefficients of the cover image coherently based on the values of DCT coefficients. It is observed that the proposed algorithm has better PSNR, Security and capacity compared to the existing techniques.


international conference on computational intelligence and communication networks | 2011

Dual Transform Technique for Robust Steganography

K B Shiva Kumar; T. Khasim; K B Raja; Sabyasachi Pattnaik; R. K. Chhotaray

Steganography enables to have a secret communication in modern information technology using public channel. In this paper, we propose Dual Transform Technique for Robust Steganography (DTTRS). The cover image is segmented into blocks of 4*4 each and Discrete Wavelet Transform (DWT) is applied on each block. In the resulting DWT coefficients, blocks of vertical band of 2*2 each are considered and Integer Wavelet Transform (IWT) is applied to get blocks of 1*1 each. The IWT is applied on vertical band of DWT of payload to generate coefficients of payload and are embedded into IWT coefficients of cover image using least significant bit replacement method. On applying IIWT and IDWT, stego image is derived. The concept of error detecting and correcting coding technique is employed to ensure more reliable communication. It is observed that the proposed algorithm has excellent PSNR, provides high level security and more robust compared to individual transform techniques.


IOSR Journal of Computer Engineering | 2012

Feature Level Fusion Based Bimodal Biometric Using Transformation Domine Techniques

Ramachandra A C; Abhilash S K; K B Raja; Venugopal K R; L M Patnaik

Bimodal biometric used to authenticate a person is more accurate compared to single biometric trait. In this paper we propose Feature Level Fusion based Bimodal Biometric using Transformation Domine Techniques (FLFBBT). The algorithm uses two physiological traits viz., Fingerprint and Face to identify a person. The Region of Interest (ROI) of fingerprint is obtained using preprocessing. The features of fingerprint are extracted using Dual Tree Complex Wavelet Transforms (DTCWT) by computing absolute values of high and low frequency components. The final features of fingerprint are computed by applying log on concatenated absolute value of high and low frequency components. The face image is preprocessed by cropping only face part and Discrete Wavelet Transforms (DWT) is applied. The approximation band coefficients are considered as features of face. The fingerprint and face image features are concatenated to derive final feature vector of bimodal biometric. The Euclidian Distance (ED) is used in matching section to compare test biometric in the database, it is observed that the values of EER and TSR are better in the case of proposed algorithm compared to individual transformation domain techniques.


international conference on computational intelligence and computing research | 2010

Biometric security system based on signature verification using neural networks

D. R. Shashikumar; K B Raja; R. K. Chhotaray; Sabyasachi Pattanaik

The signature verification is the behavioral parameter of biometrics and is used to authenticate a person. A typical signature verification system generally consists of four components: data acquisition, preprocessing, feature extraction and verification. In this paper, Biometric Security System Based on Signature Verification Using Neural Networks (BSSV) is presented. The global and grid features are combined to generate new set of features for the verification of signature. The Neural Network is used as a classifier for the authentication of a signature. The performance analysis is verified on random, unskilled and skilled signature forgeries along with genuine signatures. It is observed that FAR and FRR results are improved in the proposed method compared to the existing algorithms.


international conference on signal processing | 2015

An efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC-FFT

Satish S Bhairannawar; Sayantam Sarkar; K B Raja; K. R. Venugopal

The real time biometric systems are used to authenticate persons for various applications. In this paper, we propose an efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC-FFT. The O2D-DWT architecture is designed using only adders and shifters for high speed operation and is applied on fingerprint image to generate four sub-bands. The optimized Fast Fourier Transform (OFFT) architecture is designed by computing different twiddle factor angles using modified CORDIC processor and is applied on LL sub-band coefficients to generate final fingerprint features. The test fingerprint features are compared with features of fingerprint images in database using Euclidean Distance. It is observed that the performance of proposed architecture is better compared to existing architectures.


International Journal of Computer Applications | 2011

Hybrid Domain in LSB Steganography

K B Shiva Kumar; K B Raja; Sabyasachi Pattnaik

The maintenance of privacy and secrecy of information in modern communication is accomplished through steganographic technique. Spatial domain techniques are popular ones in image steganography. In this paper, we propose hybrid steganography (HDLS) which is an integration of both spatial and transform domains. The cover image as well as the payload is divided into two cells each. The RGB components of cover image cell I are separated and then transformed individually from spatial to transform domain using DCT/DWT/FFT and embedded in a special manner, the components of cell II retained in spatial domain itself. The proposed algorithm has better PSNR and security as compared to existing techniques.


International Journal of Computer Theory and Engineering | 2010

Template based Mole Detection for Face Recognition

Ramesha K; K B Raja; Venugopal K R; Lalit M. Patnaik

Face recognition is used for personal identification. The Template based Mole Detection for Face Recognition (TBMDFR) algorithm is proposed to verify authentication of a person by detection and validation of prominent moles present in the skin region of a face. Normalized Cross Correlation (NCC) matching, complement of Gaussian template and skin segmen tation is used to identify and validate mole by fixing predefined NCC threshold values. It is observed that the NCC values of TBMDFR are much higher compared to the existing algorithms.


international conference on computational intelligence and computing research | 2012

FPGA based Recursive Error Free Mitchell Log Multiplier for image Filters

Satish S Bhairannawar; R. Rathan; K B Raja; K R Venugopal; L M Patnaik

The Multiplier plays an important role in implementing real time Biometric systems, hence high speed with error free multipliers has to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier for image Filters. The 2×2 Mitchell log multiplier is considered and error correction term is introduced to correct error, to obtain 2×2 Error Free Mitchell Log Multiplier (EFMLM). The higher order Mitchell Log Multiplier are derived from 2×2 EFMLM using Karatsuba Ofman parallel architecture multiplier with no error. The proposed multiplier is used to design Gaussian Filter to enhance the quality of fingerprint image. The Multiplier is synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance of proposed architecture is better compared to existing architecture.


international conference on telecommunications | 2010

Combined Off-Line Signature Verification Using Neural Networks

D. R. Shashi Kumar; R. Ravi Kumar; K B Raja; R. K. Chhotaray; Sabyasachi Pattanaik

In this paper, combined off-line signature verification using Neural Network (CSVNN) is presented. The global and grid features are combined to generate new set of features for the verification of signature. The Neural Network (NN) is used as a classifier for the authentication of a signature. The performance analysis is verified on random, unskilled and skilled signature forgeries along with genuine signatures. It is observed that FAR and FRR results are improved in the proposed method compared to the existing algorithm.


Vlsi Design | 2016

An Efficient Reconfigurable Architecture for Fingerprint Recognition

Satish S. Bhairannawar; K B Raja; K. R. Venugopal

The fingerprint identification is an efficient biometric technique to authenticate human beings in real-time Big Data Analytics. In this paper, we propose an efficient Finite State Machine FSM based reconfigurable architecture for fingerprint recognition. The fingerprint image is resized, and Compound Linear Binary Pattern CLBP is applied on fingerprint, followed by histogram to obtain histogram CLBP features. Discrete Wavelet Transform DWT Level 2 features are obtained by the same methodology. The novel matching score of CLBP is computed using histogram CLBP features of test image and fingerprint images in the database. Similarly, the DWT matching score is computed using DWT features of test image and fingerprint images in the database. Further, the matching scores of CLBP and DWT are fused with arithmetic equation using improvement factor. The performance parameters such as TSR Total Success Rate, FAR False Acceptance Rate, and FRR False Rejection Rate are computed using fusion scores with correlation matching technique for FVC2004 DB3 Database. The proposed fusion based VLSI architecture is synthesized on Virtex xc5vlx30T-3 FPGA board using Finite State Machine resulting in optimized parameters.

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K. R. Venugopal

University Visvesvaraya College of Engineering

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L M Patnaik

University Visvesvaraya College of Engineering

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Lalit M. Patnaik

Indian Institute of Science

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Venugopal K R

University Visvesvaraya College of Engineering

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Sayantam Sarkar

Dayananda Sagar College of Engineering

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S. Sitharama Iyengar

Florida International University

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Satish S. Bhairannawar

SDM College of Engineering and Technology

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H C Sateesh Kumar

Sai Vidya Institute of Technology

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K R Venugopal

University Visvesvaraya College of Engineering

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