K. Chen

FELIX: a high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed.

Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

4^{\mathrm{th}}

Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between

A new approach to front-­‐end electronics interfacing in the ATLAS experiment

1\cdot 10^{14}

Evaluation of commercial ADC radiation tolerance for accelerator experiments

and

The development of the global feature extractor for the LHC Run-3 upgrade of the L1 calorimeter trigger system

5\cdot 10^{15}

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

1-MeV-n

The clock and control system for the ATLAS Liquid Argon Calorimeter Phase-I upgrade

_\textrm{eq}

Optimization on fixed low latency implementation of the GBT core in FPGA

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