K. E. J. Goh

Bilayer gate dielectric study by scanning tunneling microscopy

An advanced bilayer gate dielectric stack consisting of Sc2O3∕La2O3∕SiOx annealed in nitrogen at 300°C was studied by scanning tunneling microscopy using bias dependent imaging. By changing the sample bias, electrical properties of different layers of the dielectric stack can be studied. At a sample bias of +3.5V, the conduction band of the La2O3 layer is probed revealing a polycrystalline film with an average grain size of about 27nm, in good agreement with that determined from planar transmission electron microscopy. High conductivity at grain boundaries, due possibly to dangling bonds, can be observed in this layer, as also observed in grain boundary assisted current conduction in metal-oxide-silicon structures. Imaging at a sample bias of −4V probes the interfacial SiOx layer and an amorphouslike image of the interfacial layer is obtained.

Scanning probe microscopy for silicon device fabrication

We present a review of a detailed fabrication strategy for the realisation of nano and atomic-scale devices in silicon using phosphorus as a dopant and a combination of ultra-high vacuum scanning probe microscopy and silicon molecular beam epitaxy (MBE). In this work we have been able to overcome some of the key fabrication challenges to the realisation of atomic-scale devices including the identification of single P dopants in silicon, the controlled incorporation of P atoms in silicon with atomic precision and the minimisation of P segregation and diffusion during Si encapsulation. Recently, we have combined these results with a novel registration technique to fabricate robust electrical devices in silicon that can be contacted and measured outside the ultra-high vacuum environment. We discuss the importance of our results for the future fabrication of atomic-scale devices in silicon.

Effect of encapsulation temperature on Si:P δ-doped layers

We present a systematic study of the effect of encapsulation temperature on dopant segregation and electronic transport in Si:P δ-doped layers. We demonstrate that while limited dopant segregation and complete electrical activation can be achieved at room temperature, a δ-doped layer encapsulated at ∼250°C represents the best compromise between high electrical quality (mobility ∼61cm2V−1s−1 and phase coherence length ∼72nm at 4.2K) and minimal dopant segregation. Higher encapsulation temperatures are shown to lead to significant dopant segregation.

The use of etched registration markers to make four-terminal electrical contacts to STM-patterned nanostructures.

We demonstrate the use of etched registration markers for the alignment of four-terminal ex situ macroscopic contacts created by conventional optical lithography to buried nanoscale Si:P devices, patterned by hydrogen-based scanning tunnelling microscope (STM) lithography. Using SiO(2) as a mask we are able to protect the silicon surface from contamination during marker fabrication and can achieve atomically flat surfaces with atomic-resolution imaging. The registration markers are shown to withstand substrate heating to approximately 1200 degrees C and epitaxial overgrowth of approximately 25 nm Si. Using a scanning electron microscope to position the STM tip with respect to the markers, we can achieve alignment accuracies of approximately 100 nm, which allows us to contact buried Si:P structures. We have applied this technique to fabricate P-doped wires of different widths and measured their I-V characteristics at 4 K, finding ohmic behaviour down to a width of approximately 27 nm.

Atomic-scale silicon device fabrication

The driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce device sizes below 10 nm. In this paper we demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in combination with scanning probe lithography and high purity crystal growth. Using this process we have fabricated conducting nanoscale wires with widths down to ∼8 nm, and arrays of P-doped dots in silicon. We will present an overview of devices that have been made with this technology and highlight some of the detailed atomic level understanding of the doping process developed towards atomically precise devices.

Narrow, highly P-doped, planar wires in silicon created by scanning probe microscopy

We demonstrate the use of a scanning tunnelling microscope (STM) to pattern buried, highly planar phosphorus-doped silicon wires with widths down to the sub-10 nm level. We confirm the structural integrity of these wires using both buried dopant imaging techniques and ex situ electrical characterization. Four terminal I–V characteristics at 4 K show ohmic behaviour for all wires with resistivities between 1 and 24 × 10−8 Ω cm. Magnetotransport measurements reveal that conduction is dominated by disordered scattering with quantum corrections consistent with 2D weak localization theory. Our results show that these quantum corrections become more pronounced as the electron phase coherence length approaches the width of the wire.

Enhancing electron transport in Si:P delta-doped devices by rapid thermal anneal

We address the use of rapid thermal anneal (RTA) to enhance electron mobility and phase coherent transport in Si:P δ-doped devices encapsulated by low temperature Si molecular beam epitaxy while minimizing dopant diffusion. RTA temperatures of 500–700°C were applied to δ-doped layers encapsulated at 250°C. From 4.2K magnetotransport measurements, we find that the improved crystal quality after RTA increases the mobility/mean free path by ∼40% and the phase coherence length by ∼25%. Our results suggest that the initial capping layer has near optimal crystal quality and transport improvement achieved by a RTA is limited.

Using patterned H-resist for controlled three-dimensional growth of nanostructures

We present a study addressing the effectiveness of a monolayer of hydrogen as the lithographic resist for controlled three-dimensional (3D) growth of nanostructures on the Si(100) surface. Nanoscale regions on the H-terminated Si(100) were defined by H-desorption lithography via the biased tip of a scanning tunneling microscope (STM) to create well-defined regions of surface “dangling bonds,” and the growth of 3D nanostructures within these regions was achieved using a simultaneous disilane deposition and STM H-desorption technique. We demonstrate that 3D growth is strongly confined within STM depassivated regions while unpatterned H:Si(100) regions are robust against adsorption of the precursor molecules.

Electronically transparent graphene barriers against unwanted doping of silicon.

Diffusion barriers prevent materials from intermixing (e.g., undesired doping) in electronic devices. Most diffusion barrier materials are often very specific for a certain combination of materials and/or change the energetics of the interface because they are insulating or add to the contact resistances. This paper presents graphene (Gr) as an electronically transparent, without adding significant resistance to the interface, diffusion barrier in metal/semiconductor devices, where Gr prevents Au and Cu from diffusion into the Si, and unintentionally dope the Si. We studied the electronic properties of the n-Si(111)/Gr/M Schottky barriers (with and without Gr and M=Au or Cu) by I(V) measurements and at the nanoscale by ballistic electron emission spectroscopy (BEEM). The layer of Gr does not change the Schottky barrier of these junctions. The Gr barrier was stable at 300 °C for 1 h and prevented the diffusion of Cu into n-Si(111) and the formation of Cu3Si. Thus, we conclude that the Gr is mechanically and chemically stable enough to withstand the harsh fabrication methods typically encountered in clean room processes (e.g., deposition of metals in high vacuum conditions at high temperatures), it is electronically transparent (it does not change the energetics of the Si/Au or Si/Cu Schottky barriers), and effectively prevented diffusion of the Cu or Au into the Si at elevated temperatures and vice versa.

Low temperature nanoscale electronic transport on the MoS2 surface

Two-probe electronic transport measurements on a Molybdenum Disulphide (MoS2) surface were performed at low temperature (30 K) under ultra-high vacuum conditions. Two scanning tunneling microscope tips were precisely positioned in tunneling contact to measure the surface current-voltage characteristics. The separation between the tips is controllably varied and measured using a high resolution scanning electron microscope. The MoS2 surface shows a surface electronic gap (ES) of 1.4 eV measured at a probe separation of 50 nm. Furthermore, the two- probe resistance measured outside the electronic gap shows 2D-like behavior with the two-probe separation.