K. F. Galloway

Temperature-Induced Rebound in Power MOSFETs

Enhancement-mode n-channel power MOSFETs were investigated for rebound. They received 300 krad(Si) gamma dose under positive gate bias with source and drain grounded. The irradiated transistors were thermally annealed with all terminals shorted or under positive gate bias with drain and source shorted, at temperatures from 60°C to 150°C. Threshold voltage rebound was observed for some transistor types under certain experimental conditions.

Radiation Dose Due to Electron-Gun Metallization Systems

Electron beam evaporation is often selected as a method for depositing the gate metal for metal-oxidesemiconductor (MOS) devices. X-rays generated by electron impact on the metal to be evaporated may produce damage in the gate oxide. Several experimenters have reported that radiation-hardened MOS devices metallized in electron-gun systems appear to degrade at a faster rate than devices fabricated identically except for the metallization technique used. In order to examine ways of minimizing the damage introduced by electron beam systems and to develop a basis for understanding the physical phenomena observed, the physics of the x-ray energy deposition during the metallization process was explored. Details of the calculational procedure, the data necessary to calculate the x-ray absorbed dose in the oxide layer due to the electron-gun deposition of aluminum and chromium, and the calculations are presented. The results of experimental measurements of the x-ray dose are included for comparison. The implications of the results including the differences in the radiation susceptibility of MOS devices prepared with different gate metals are discussed.

VLSI Processing, Radiation, and Hardening

Process-induced radiation damage to silicon dioxide films is expected to be commonplace for VLSI circuit fabrication. This might be expected to be most serious for the production of radiation-hardened VLSI. In this paper, the oxide damage due to ion processing is reviewed and the radiation levels associated with advanced lithographic techniques are estimated. Implications for radiation-hardened VLSI circuits are considered.

Radiation-Induced Interface Traps in Power Mosfets

Methods for estimating radiation-induced interface trap density from the current-voltage (I-V) characteristics of MOSFETs are described and applied to commercially available power MOSFETs. The power MOSFETs show severe degradation on radiation exposure with the effects of positive oxide trapped charge dominating; however, interface trap buildup is significant. The results are compared to experimental measurements available on other technologies.

Characteristics of the Breakdown Voltage of Power MOSFETs after Total Dose Irradiation

The effects of total dose irradiation on the breakdown voltage of p-channel power MOSFETs are examined. Although breakdown voltage for p-channel devices increased at higher dose levels, as expected, some devices exhibited an initial decrease in breakdown at very low levels of total dose. The interaction of ionizing radiation effects with the junction termination methods designed to increase the voltage at which breakdown occurs is analyzed.

Important Considerations for SEM Total Dose Testing

The kilovolt electron beam utilized in a scanning electron microscope has been of interest as a tool for total dose screening of semiconductor devices for hardness assurance because of its convenience and because devices can be selectively irradiated directly at the wafer level. A number of factors such as the depth-dose distribution of kilovolt electrons, the dose-rate, uniformity of exposure, and device biasing must be considered when applying this technique. This paper is devoted to these and other aspects of SEM total dose testing.

Radiation Damage to Integrated Injection Logic Cells

The effects of neutron and total dose gamma irradiations on the electrical characteristics of an integrated injection logic (I2L) cell and an I2L multiple inverter circuit were investigated. These units were designed and fabricated to obtain circuit development information and did not have radiation hardness as a goal. The following parameters of the test structures were measured as a function of total dose and neutron fluence: the dc common-base current gain of the lateral pnp transistor; the dc common-emitter current gain of the vertical npn transistor; the forward current-voltage characteristics of the injector-substrate junction, and the propagation delay versus power dissipation per gate for the multiple inverter circuit. The limitations of the present test structures in a radiation environment and possible hardening techniques are discussed.