K Hari Kishore

Bit wise and delay of vedic multiplier

The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

Improvement of the efficiency of booth multiplier

Objective: To Improve the performance of Booth Multiplier and reduce power consumption. Method: The most essential form of multiplication consists of framing the result of two unsigned (positive) binary numbers. Finding: Booth Multiplier consists of pre-defined table. According to this algorithm, multiplication of two numbers x and y (x*y) is same as multiplication of y and x (y*x). At times this rule fails due to which we modify the logic by converting the decimal number in to 4 bit binary number and appending (n-2) zeros at most significant bit and one zero at least significant bit. Improvement: By using this method we can get accurate results in multiplication by multiplying like (x*y) and (y*x).

Diabetic retinopathy through retinal image analysis: A review

In this paper, the recent advancement in the Digital Image Processing Aspects in the Diabetic Retinopathy (DR) were been discussed. The major approaches in DR are categorized into four classes namely Preprocessing, Optic Disk Detection, Blood Vessel Extraction and supervised classification. The optic disk, blood vessels and exudates gives more analytical details about the retinal image, segmentation of those features are very important. Further these approaches are classified into finer classes based on the methodologies accomplished in the respective schemes. The details of the database those used for testing the proposed algorithms is also illustrated in this paper. The details of performance metrics such as accuracy, sensitivity, specificity, precision, recall and F-measure are also discussed through their mathematical expressions.

Efficient and high speed key-independent AES-based authenticated encryption architecture using FPGAs

Data manipulations are made with the use of communication and networking systems. But at the same time, data integrity is also a needed and important property that must be maintained in every data communicating systems. For this, the security levels are provided with cryptographic primitives like hash functions and block ciphers which are deployed into the systems. For efficient architectures, FPGA-based systems like AES-GCM and AEGIS-128 plays in the best part of the re-configurability, which supports the security services of such communication and networking systems. We possibly focus on the performance of the systems with the high security of the FPGA bit streams. GF (2) multiplier is implemented for authentication tasks for high-speed targets. And also, the implementations were evaluated by using vertex 4.5 FPGA’s

Design of low power 10GS/s 6-Bit DAC using CMOS technology

A Low power 6-bit R-2R ladder Digital to Analog Converter is presented in this paper. Here the R-2 R network designed using resistors with only two values-R and 2xRand the switch is designed by using both NMOS and PMOS Transistors. This Digital to Analog Converters operated with low voltage, by applying dynamic threshold MOSFET (DTMOS) logic. This design achieved less INL and DNL which is 0.3 and 0.06 respectively. Power supply required to operate this device is only 1V with10GHzconversion rate. This design is implemented by using 0.18μm CMOS technology.