K. J. Chang

The novel stress simulation method for contemporary DRAM capacitor arrays

The increasing of aspect ratio in DRAM capacitors causes structural instabilities and device failures as the generation evolves. Conventionally, two-dimensional and three-dimensional models are used to solve these problems by optimizing thin film thickness, material properties and structure parameters; however, it is not enough to analyze the latest failures associated with large-scale DRAM capacitor arrays. Therefore, beam-shell model based on classical beam and shell theories is developed in this study to simulate diverse failures. It enables us to solve multiple failure modes concurrently such as supporter crack, capacitor bending, and storage-poly fracture.

Process Margin Analysis and Yield Enhancement Through Statistical Topography Simulation

One of the major challenges in deep submicron semiconductor era is to control the increase of variations due to decreasing in feature size. Currently, Design for Manufacturing (DFM) method enables to optimize layouts reducing the influence of process variations on circuit [1]. In this paper, we investigated the process margin analysis methods which are related to process defects of high aspect ratio (HAR) contact and short failures between lines. From this methodology, yield limiting process failures are identified and nano-scale defects in cells are virtually monitored without destructive method. This novel simulation methodology makes it possible to estimate the number of void defects of floating gate in Flash memory and predict Breakdown Voltage (BV) of the capacitor in DRAM. As a result, the defect level which is related yield has been decreased from 42% to 2.1% in 60nm Flash device and BV of capacitor has been virtually monitored in 80nm DRAM device.