K. Swientek

Forward instrumentation for ILC detectors

Two special calorimeters are foreseen for the instrumentation of the very forward region of the ILC detector, a luminometer designed to measure the rate of low angle Bhabha scattering events with a precision better than 10?3 and a low polar angle calorimeter, adjacent to the beam-pipe. The latter will be hit by a large amount of beamstrahlung remnants. The amount and shape of these depositions will allow a fast luminosity estimate and the determination of beam parameters. The sensors of this calorimeter must be radiation hard. Both devices will improve the hermeticity of the detector in the search for new particles. Finely segmented and very compact calorimeters will match the requirements. Due to the high occupancy fast front-end electronics is needed. The design of the calorimeters developed and optimised with Monte Carlo simulations is presented. Sensors and readout electronics ASICs have been designed and prototypes are available. Results on the performance of these major components are summarised.

Measurements of Matching and High Count Rate Performance of Multichannel ASIC for Digital X-Ray Imaging Systems

We present the measurements of matching and high count rate performance of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 mum CMOS process and its total area is 3900 times 5000 mum2. The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures a low spread of discriminator effective threshold, namely 0.4 mV at one sigma level. The mean gain in the multichannel ASIC is 54 muV/el, with a good uniformity from channel-to-channel (sd/mean ap 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz average rate of input signals.

Contrast cancellation technique applied to digital x-ray imaging using silicon strip detectors.

Dual-energy mammographic imaging experimental tests have been performed using a compact dichromatic imaging system based on a conventional x-ray tube, a mosaic crystal, and a 384-strip silicon detector equipped with full-custom electronics with single photon counting capability. For simulating mammal tissue, a three-component phantom, made of Plexiglass, polyethylene, and water, has been used. Images have been collected with three different pairs of x-ray energies: 16-32 keV, 18-36 keV, and 20-40 keV. A Monte Carlo simulation of the experiment has also been carried out using the MCNP-4C transport code. The Alvarez-Macovski algorithm has been applied both to experimental and simulated data to remove the contrast between two of the phantom materials so as to enhance the visibility of the third one.

DEDIX - Development of Fully Integrated Multichannel ASIC for High Count Rate Digital X-ray Imaging Systems

We present the development of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 mum CMOS process and its total area is 3400 times 5000 mum2. The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures the low spread of effective threshold of discriminators at 0.4 mV on one sigma level. The mean gain in the multichannel ASIC is 54 muV/el, with a good uniformity from channel to channel (sd/mean = 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz of average rate of input signals.

Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade

We present the test results of the ABCN-25 front end chip implemented in CMOS 0.25 μm technology and optimised for the short, 2.5 cm, silicon strips intended to be used in the upgrade of the ATLAS Inner Detector. We have obtained the full functionality of the readout part, the expected performance of the analogue front-end and the operation of the power control circuits. The performance is evaluated in view of the minimization of the power consumption, as the upgrade detector may contain up to 70 million of channels. System tests with different power distribution schemes proposed for the future tracker detectors are possible with this chip. The ABCN-25 ASIC is now serving as the prototype readout chip in the developments of the modules and staves for the upgrade of the ATLAS Inner Detector.

A general purpose multichannel readout system for radiation detectors

The design and performance of a multichannel readout system for radiation detectors are presented. The developed 32-channel prototype system comprises fast, low-noise, front-end followed by a 10-bit multichannel digitizer and on-board FPGA data concentrator, processing the stream of digitized data with up to 6.4 Gbps rate. The operation of the whole system is managed by a microcontroller. The system can work in self-triggering mode or can be triggered externally. The implemented trigger mechanism allows for elaborate event filtering and selection of data to be transmitted to the host through the USB interface. A wide spectrum of measurements showing and quantifying the key system parameters like data transmission rate and event rate, noise, and gain are presented to prove the correct system performance. To increase the power efficiency in experiments with a non-continuous beam structure, a power pulsing mechanism is implemented and verified experimentally.

A power scalable 10-bit pipeline ADC for Luminosity Detector at ILC

The design and measurement results of a power scalable 10-bit pipeline ADC developed for the luminosity detector at the future International Linear Collider (ILC) are discussed. The prototype is designed and fabricated in 0.35 ?m CMOS technology. A wide spectrum of measurements of static (INL 58 dB, SINAD ~ 58 dB) parameters are performed to understand and quantify the circuit performance. The ADC works for sampling rates from 1 kS/s to 25 MS/s covering more than four orders of magnitude. In most of the range power consumption scales linearly with sampling rate with a factor of 0.85 mW/MS/s. With ILC beam structure and sampling rate of about 3.5 MS/s, using the implemented in ASIC power switching off feature, an average power consumption of about 15 ?W per channel may be obtained. The ADC layout is drawn with a constant pitch of 300 ?m to facilitate a multichannel implementation.

Design and performance of the ABCN-25 readout chip for ATLAS Inner Detector Upgrade

We present the design and performance of the ABCN-25 readout chip implemented in 0.25 μm CMOS technology. The front-end design has been optimized for the short, 2.5 cm, silicon strips foreseen in the upgrade of the ATLAS Inner Detector. The core of the readout architecture includes binary front-end, two levels of data buffering, data compression and data serializing circuitry, and is similar to the architecture of the ABCD3T chip used in the present ATLAS SCT detector. In order to ensure required radiation hardness the hardening by layout technique has been used and SEU detection and correction circuitry have been added. The design includes on-chip power management circuitry comprising two types of shunt regulators and a serial regulator. This circuitry makes the ABCN-25 chip compatible with recent developments in the area of power distribution systems for the inner trackers in the SuperLHC environment and in particular with serial powering of the detector modules. The chip has been fabricated in 0.25 μm CMOS technology and full functionality has been obtained. The critical design aspects and performance of the analog and digital circuits will be presented and discussed.

A 10-Bit Multichannel Digitizer ASIC for Detectors in Particle Physics Experiments

The design and measurement results of a multi-channel power scalable 10-bit digitizer ASIC developed for the luminosity detector at the future linear colliders (ILC/CLIC) are discussed. The 8 channel prototype with different modes of output data serialization was designed and fabricated in a 0.35 μm CMOS technology. The ASIC works for sampling rates from about 10 kS/s to 25 MS/s (50 MS/s in single channel mode) allowing linear scaling of ADCs and serializer power consumption (0.8 mW/MS/s ADC core, 1.2 mW/MS/s total per channel). A wide spectrum of static and dynamic measurements confirm very good ADC resolution (ENOB = 9.7 bits), excellent channel uniformity and negligible crosstalk. To profit from non-continuous detector operation in linear collider experiments and to save power consumption, fast periodic power pulsing is implemented.

X-ray imaging with a silicon microstrip detector coupled to the RX64 ASIC

A single photon counting X-ray imaging system, with possible applications to dual energy mammography and angiography, is presented. A silicon microstrip detector with 100 mm pitch strips is coupled to RX64 ASICs, each of them including 64 channels of preamplifier, shaper, discriminator and scaler. The system has low noise, good spatial resolution and high counting rate capability. Results on energy resolution have been obtained with a fluorescence source and quasi-monochromatic X-rays beams. Preliminary images obtained with an angiographic phantom are presented.