K.T. Lau

Approximate adder for low-power computations

ABSTRACT In present-day VLSI technology, errors cannot be avoided and it is not always feasible to overcome all errors. An attempt to get rid of all errors results in excessive power consumption and also slows down the system. In this article, a novel adder circuit has been presented (Imprecise Adder Circuit) that produces imperfect results but consumes lower power and is faster than traditional adders. The 16-bit adder designed has been divided into four 4-bit full adder blocks. All the adder circuits were designed with a 65-nm CMOS technology. The software CADENCE was used for designing and later for the post design simulations.

Design of Low Power CMOS Parallel Prefix Adder Cell

Addition is the basic operation in many modern electronic applications. As the fastest adder, parallel prefix adder is of most interest for many circuit designers. For the past few decades, supply voltage and the size of transistors have been reduced tremendously. With more and more transistors being integrated on one single chip, the power issue must be taken care of. Low power adder has been studied for years and many solutions are proposed. In this paper, a new circuit is designed at transistor level. The proposed circuit cell employs transmission gate logic and a MUX-based structure. Simulations are conducted using Cadence® Virtuoso Spectre Simulator. The result shows that the new adder demonstrates a better performance in terms of power dissipation, which saves more than 5% energy compared with Conventional CMOS logic adders with different word length.

LOW POWER ADIABATIC PROGRAMMABLE LOGIC ARRAY WITH SINGLE CLOCK IAPDL

A novel implementation of a low power adiabatic PLA with a single power clock (IAPDL-SC PLA) is presented. The isolation transistor in the AND array is removed. The power clock is shared by the AND array and the OR array. In this way, the proposed PLA not only saves the device components but also reduces the power consumption. For 3 V VDD and 200 MHz power clock frequency, the simulation results using Hspice show that the power saving is 79.48% compared to dynamic CMOS PLA, 69.34% compared to APDL PLA, and 40.40% compared to IAPDL PLA. For the 5 × 8 × 4 PLA design, the device saving is 30.77% compared to APDL PLA and 12.90% compared to IAPDL PLA. The diodes are the critical components for all the technology designs. Current simulation is based on 0.8 μm process and the power consumption can be further reduced using the more downsized technology designs.