K. V. Padmaja

Understanding the neural mechanism of sleep using wavelets and multifractal techniques

Dynamical properties of large ensembles of neurons in the brain during sleep are found to be highly complex; therefore, nonlinear methods have found application in the analysis of random looking EEG signals. Here we have addressed the issue of the transition process from NREM to REM and vice versa using wavelet based multifractal formalism in healthy humans. We have used the technique based on wavelet transform modulus maxima (WTMM) to detect the irregularity in the structural pattern of sleep. The filtered sleep EEG data has been subjected to WTMM, the Singularity spectrum and the Hurst exponent has been computed using the Wavelab 8.5 toolbox. The results show graphically increasing bifurcations during the Non-REM to REM transitions. The narrow width of the multifractal spectrum indicate the REM state which further indicate the presence of many autonomous zones in the REM process. In Non-REM there are fewer bifurcations and the bandwidth of the multifractal spectrum is broad indicating the presence of a single large source contributing to the Non-REM process. The Hurst exponent for the REM sleep is found to be lower than the Hurst exponent for the Non-REM sleep, which can be used as an indicator of the transitions. Our findings show that the sleep transitions may be attributed to an increasing level of bifurcations and collapses that happen with an intermittent drive or force from the pontine and the brain stem structures.

An indigenous PPG acquisition system using monolithic photo-detector OPT101

Photoplethysmograph is an optical procedure used to determine the physiological parameters identified with cardiovascular system. This paper focuses on the design of PPG acquisition system with reflectance type of sensor circuit to extract the features such as systolic peak, diastolic peak and dicrotic notch. The designed system is tested on 50 subjects of different age groups and the amplitude of PPG signal after signal conditioning ranges between 5 to 8 V. The analysis on distortion free PPG signal resulted in parameters such as augmentation index, reflection index and stiffness index. The designed system is more reliable for motion artefacts.

Performance analysis of time domain and frequency domain equalizer for ADSL

Cross Talk (NEXT, FEXT), and Inter symbol interference (ISI) degrade the performance of wire line communication system. Equalizer plays a big role in the performance improvement. Zero Forcing (ZF) and Least Mean Square (LMS) algorithm for TDE (time domain equalizer) and FDE (frequency domain equalizer) has been used for minimization of cross talk and ISI. In this paper simulation of ADSL (Asynchronous Digital Subscriber Line) channel modeling, NEXT (DSL disturber) modeling, LMS and Zero forcing algorithm are done in MATLAB. Comparison between symbol space equalizer and fractionally space equalizer is presented in the form of symbol error rate. Result shows the performance of LMS algorithm is better than ZF algorithm.

Performance of Zero forcing pre-coder for vectored DSL

This paper deal with the performance analysis of vectored DSL in terms of the computational complexity and practical implementation on DSP processor. Paper is more specific for the design of diagonalizing pre-coder in downstream transmission of vectored DSL. Different algorithms for the design of linear and nonlinear pre-coders have been proposed in the past. All of these pre-coders are either highly complex in design or they give poor performance in terms of bit rate. As the cost of the customer premises modem is an important issue, any technique that can minimize the complexity of the system is extremely beneficial. In this paper performance in terms of execution time for basic model and diagonalizing pre-coder of vectored DSL is been analyzed using DSK 6713 a digital signal 32 bit, floating point processor. The clock frequency of mention processor is considered as 250 MHz. This processor has advanced very long instruction word (VLIW) architecture, with performance of up-to 2400 (532) million instructions per second. The execution time of the processor is compared with the Matlab profiler function.

Dual latency operation in VDSL2 with downstream power back off

The main advantage of down stream power back off (DPBO) in VDSL2 is coexistence with ADSL. The ADSL link bit error rate (BER) will not get affected by introducing VDSL2 in the same binder. In this paper we present a new scheme that partitions the tones over the two latency paths based on signal-to-noise (SNR) with DPBO included in the computation. The bit loading is done from the obtained SNR profile using the standard rate adaptive water filling algorithm. The data rate of the VDSL2 system is calculated by realigning the tone loading after accounting for the fractional bits. Simulation results include bit loading pattern and data rates for the two paths with DPBO. It is further implemented on the TMS DSP processor 6713 and results hence obtained are found to match with the simulation results.

Realization of Adaptive Filters for NEXT Crosstalk Mitigation in Two Wire ADSL on DSP

Adjacent systems within a cable binder that transmit or receive data in the same frequency range can create crosstalk interference. Crosstalk canceller plays a key role in achieving high bit rates in wire line multicarrier asymmetric digital subscriber line (ADSL) systems in this paper we introduce two filters for NEXT mitigation to improve signal to noise ratio(SNR) at the input of the receiver which improves data rate. An adaptive filter using LMS, NLMS and RLS algorithms to eliminate the effect of NEXT is designed. Filter simulation was done in Matlab environment and also implemented on TMS 320C 6713 DSP. An analysis of the receiver output with and without filter is presented for various lengths. Results presented shows an improvement in data rate with this filter.