Kabiraj Sethi

An Improved Squaring Circuit for Binary Numbers

In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.

Multiplier less high-speed squaring circuit for binary numbers

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth’s algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

A low power noise cancelling LNA for UWB receiver front end

This paper presents the design of a low noise amplifier (LNA) for the ultra wideband (UWB) signals which lies in the frequency range 3.1-10.6 GHz. This method uses resistive feedback gain enhanced noise cancelling technique. It is an inductor less LNA design which consumes less power and improves the noise Fig. By using this technique, we achieve a power gain of 10.7 dB, a noise Fig. of 2.2 dB at 4.8 GHz and an IIP3 of -2.9 dBm. The power consumed by the circuit is 8.3 mW. The simulated results demonstrate that the proposed LNA has the largest bandwidth, the lowest power consumption and lowest noise Fig. among the inductorless wideband LNAs found in the literature.

Design & performance analysis of Strained-Si NMOSFET using TCAD

Geometric Scaling and high channel doping incorporate loss in mobility. To compensate this, substrate engineering innovations like SOI(Silicon On Insulator) and strained silicon technologies are introduced. In this paper NMOS is designed on Strained Si/relaxed Si0.8Ge0.2 heterostructure using TCAD. Electrical analysis of Strained-Si nMOSFET has been done by the ATLAS 2D simulator using low field Arora mobility model. A mobility enhancement factor of 2.6 and transconductance enhancement of 100% at low voltage, compared to that of unstrained -Si control device at room temperature(300K) achieved in this work. Parasitic gate capacitance, the reason for the rise in the delay time has been reduced in the range of 10-15 F.

Design of High Gain and Low Noise CMOS Gilbert Cell Mixer for Receiver Front End Design

This paper presents the design of a low noise CMOS Gilbert cell mixer in 180 nm technology with the help of cadence tool. The switched biasing technique is used to improve the noise performance by splitting the tail current source into two small transistors. The proposed mixer produces a simulated conversion gain (CG) of 9.95 dB with a noise figure (NF) of about 8.12 dB. The supply voltage required for the circuit is 1.8 V with a power consumption of 3.5 mW. The layout of the present design is also given here. This design results better performance in the conversion gain, noise figure and power consumption than the conventional mixer design available in the literature. Hence, this design is a suitable block for receiver front end design for wireless systems.

Design and Implementation of a New Program Address Generator Unit in a DSP Processor

This paper presents the design and implementation of a new Program Address Generator (PAG) unit, which is a part of Program Control Unit (PCU) well suited for DSP Processors. This would be compatible with DSP56002 (DSP Processor from Motorola) at instruction level. The PAG provides hardware dedicated to support loops, which are frequent constructs in DSP algorithm. The proposed architecture of PAG has been modeled, verified and synthesized using VHDL description and synthesis tools. It is found that the proposed AGU generates actual address for program memory as per the given set of inputs. Simulation results are compared with the theoretical data and found correct.