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Kai Koji

Panasonic

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Publication

Featured researches published by Kai Koji.

IEICE technical report. Computer systems | 1998

Dynamically Variable Line-Size Caches Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs

井上 弘士; Inoue Koji; 甲斐 康司; Kai Koji; 村上 和彰; Murakami Kazuaki

Technical report of IEICE. ICD | 1997

A DRAM Refresh Architecture for Merged DRAM/Logic LSIs

Kai Koji; 甲斐 康司; 大澤 拓; Ohsawa Taku; Murakami Kazuaki; 村上 和彰

情報処理学会研究報告. EMB, 組込みシステム | 2009

Predicting Cache Miss Rates via Simulation Results Reuse

Ono Takatsugu; 小野 貴継; 井上 弘士; Inoue Koji; 村上 和彰; Murakami Kazuaki; 甲斐 康司; Kai Koji

Archive | 2006

Datenübertragungssystem unter Verwendung einer Bitumkehrung

Inoue Akihiko; Kai Koji; Toujima Masayoshi; Hashimoto Takashi

Archive | 2006

Cache-Speicher-Vorrichtung mit variablem Blockgrößen-Mechanismus

Kai Koji; Inoue Koji; Murakami Kazuaki

Technical report of IEICE. ICD | 2000

Performance and Energy Evaluation of a Dynamically Variable Line-Size Cache

井上 弘士; Inoue Koji; 甲斐 康司; Kai Koji; 村上 和彰; Murakami Kazuaki

Archive | 1999

Cache storage system with a variable mechanism for blocks sizes

Kai Koji; Inoue Koji; Murakami Kazuaki

Technical report of IEICE. VLD | 1998

Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs

大澤 拓; Ohsawa Taku; 甲斐 康司; Kai Koji; 村上 和彰; Murakami Kazuaki

Technical report of IEICE. ICD | 1997

On-chip Memorypath Architectures for PPRAM-type LSIs

井上 弘士; Inoue Koji; Miyajima Hiroshi; 宮嶋 浩志; Kai Koji; 甲斐 康司; 村上 和彰; Murakami Kazuaki

Archive | 1994

Verfahren und Einrichtung zur Signalformung von Paketdaten

Urabe Yoshio; Koga Shouichi; Takai Hitoshi; Kai Koji; Yamasaki Hidetoshi

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Collaboration

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Murakami Kazuaki

Kyushu University

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Inoue Koji

Kyushu University

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村上 和彰

Kyushu University

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井上 弘士

Kyushu University

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Ohsawa Taku

Kyushu University

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Hashimoto Takashi

Panasonic

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Inoue Akihiko

Panasonic

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Koga Shouichi

Panasonic

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Miyajima Hiroshi

Kyushu University

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Ono Takatsugu

Kyushu University

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