Kai Luo

Asymmetric bidirectional view synthesis for free viewpoint and three-dimensional video

Virtual view synthesis is a key technology for future free viewpoint video and three-dimensional video applications. A novel asymmetric bidirectional view synthesis method is proposed for multi-view video plus depth based systems. An intermediate virtual view is synthesized based on two adjacent reference views, which are termed as the main view and the auxiliary view. The main view contains two-dimensional color images plus per-pixel depth information. The auxiliary view only contains two-dimensional color images without depth information. The basic depth-image-based rendering technique is firstly optimized with a distance- and- depth weighted algorithm to solve the visibility and resampling problems and then applied in the following four-step view synthesis process. First, extract the occluded color data from the auxiliary view. Second, generate the corresponding occluded depth data. Then, generate two candidate virtual view images based on the main view information and the occluded information. Last, asymmetrically synthesize the two candidate virtual view images to generate the final virtual view image. Theoretical analysis and experimental results show that the proposed method can generate intermediate virtual views with high image quality.

System-on-chip design for a statistical decoder

In this paper, we propose a system-on-chip software hardware co-design for a statistical decoder. We use the context-based adaptive binary arithmetic decoder (CABAC decoder) used in the High profile of the H.264/AVC video coding standard as a design example. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. It is capable of decoding one bin per clock cycle at high clock frequencies while maintaining a slim hardware footprint. Compared to existing statistical decoders, this design is aimed for a fast and compact IP core, well verified with standard video test sequence, and ideal for a SoC implementation.

Design and implementation of twin transport stream demultiplexor in HDTV decoder

A new architecture for transport stream demultiplexer (TS Demux) in high definition television (HDTV) decoder is presented in this paper, which is able to demultiplex two TS inputs synchronously. We have pursued a hardware-based design that controlled by the software to yield high performance in the least silicon area. The key parts of the architecture, including PID filter, section filter and Memory Control Unit (MCU), are shared by the two TS inputs in terms of a time slice. Owing to the elaborate shared mechanism, our design is efficient to support more tremendous functions with less resource compared to the current scheme.

A parallel serial filtering mixed advanced ID interpolation architecture for AVS

This paper presents an advanced ID interpolation architecture for AVS video coding standard. Previous approaches have demerit of low data throughput. The proposed design parallel filters the horizontal data and serial filters the vertical data, thus greatly improve the throughput. Experimental result shows it outperforms conventional designs in processing cycle and chip area. The prototype design costs 26.2 K gates when synthesized at 108 MHz using 0.18 mum CMOS technology.

Updating strategy based architecture for reference picture management in H.264/AVC

Reference Picture Management is complex for hardware implementation. This paper presents an updating strategy for reference picture lists generation by Prime Lists maintenance. Straight insert sorting is used to find out picture insert index. Segmentation and FFA algorithms are applied to quickly adjust frame and field in Initialization stage. Further more, caching technique is used to accelerate index query which results in cycle reduction for every inter-prediction block decoding. Experiment shows the design costs 21.6 K gates under constraint of 5 ns plus a 34 words, 70-bit wide single port register file. The updating strategy based architecture has active meaning to the hardware RPM design in H.264 decoder.