Kai Weber

Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods

In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and -correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designs

Automatic Formal Verification of Fused-Multiply-Add FPUs

In this paper we describe a fully-automated methodology for formal verification of fused-multiply-add floating point units (FPU). Our methodology verifies an implementation FPU against a simple reference model derived from the processors architectural specification, which may include all aspects of the IEEE specification including denormal operands and exceptions. Our strategy uses a combination of BDD- and SAT-based symbolic simulation. To make this verification task tractable, we use a combination of case-splitting, multiplier isolation, and automatic model reduction techniques. The case-splitting is defined only in terms of the reference model, which makes this approach easily portable to new designs. The methodology is directly applicable to multi-GHz industrial implementation models (e.g., HDL or gate-level circuit representations) that contain all details of the high-performance transistor-level model, such as aggressive pipelining, clocking, etc. Experimental results are provided to demonstrate the computational efficiency of this approach.

Functional verification of the IBM system z10 processor chipset

This paper describes the comprehensive verification effort of the IBM System z10™ processor chipset, which consists of the z10™ quad-core central processor chip and the companion z10 symmetric multiprocessor (SMP) chip. The z10 processor chipset represented a significant redesign of its predecessor and thus presented a new challenge to ensure complete functional correctness of the product before the construction of actual system hardware. The z10 microprocessor pipeline was completely redesigned to support a doubling of the operating frequency. It also includes new hardware performance features, such as enhanced branch prediction, a reoptimized cache hierarchy, hardware-based prefetching, and a hardware implementation of decimal floating-point arithmetic in IEEE formats. In addition, there were significant hardware changes in the SMP storage hierarchy for optimized data latency performance. These changes include a new system topology, interprocessor book protocol, larger SMP size, and various aggressive cache ownership schemes. Key verification innovations are described, and a direct relationship to improved z10 system quality is provided for most cases.

Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We define a multiplier description language which abstracts from low-level optimizations and which can model a wide range of common implementations at a structural and arithmetic level. The correctness of the created model is established by bit level transformations matching the model against a standard multiplication specification. The model is also translated into a gate netlist to be compared with the full-custom implementation of the multiplier by standard equivalence checking. The advantage of this approach is that we use a high level language to provide the correlation between structure and bit level arithmetic. This compares favorably with other approaches that have to spend considerable effort on extracting this information from highly optimized implementations. Our approach is easily portable and proved applicable to a wide variety of state-of-the-art industrial designs.

Superprocessors and Supercomputers

In this article, we describe current state-of-the art processor designs, the design challenges faced by technology, and design scaling slow-down, problems with the new design paradigms and potential solutions as well as longer-term trends and requirements for future processors and systems. With technology and design scaling slowing down, the processor industry rapidly moved from high-frequency designs to multi-core chips in order to keep delivering the traditionally expected performance improvements. However, this rapid paradigm change created a whole new set of problems for the efficient usage of these multi-core designs in large-scale systems. Systems need to satisfy an increasing demand in throughput computing while at the same time still growing single-thread performance significantly. The increase in processor cores poses severe challenges to operating system and application development in order to exploit the available parallelism. It also requires new programming models (e.g. OpenCL*). Furthermore, commercial server systems are more and more enriched with special-purpose processors because these specialty engines are able to deliver more performance within the same power envelope than general-purpose microprocessors for certain applications. We are convinced that future processors and systems need to be designed with tight collaboration between the hardware and software community to ensure the best possible exploitation of physical resources. In the post-exponential growth era, hardware designs need to heavily invest in programmability features in addition to the traditional performance improvements.