Kamran Azadet

Equalization and FEC techniques for optical transceivers

In this tutorial paper, we present the application of well-known DSP techniques used in lower speed wireline and wireless applications, to high-speed optical communications. After an introduction on todays optical network architecture and typical optical channel impairments, we study techniques such as fiber equalization, maximum likelihood detection, and current and next generations Forward Error Correction (FEC), with special emphasis on VLSI implementation.

Frequency-interleaving technique for high-speed A/D conversion

This paper introduces a concept of analog-to-digital conversion for very high-speed applications. Like the time-interleaving conversion, this method uses different conventional ADCs (channels), which work in parallel, but the approach is different. The basic principle is close to techniques used in signal processing, such as the discrete Fourier transform (DFT) and sub-band coding. Because of its low sensitivity to sampling-clock jitter; this technique can achieve a 6 bit effective accuracy up to the Nyquist frequency.

High-speed reduced-state sequence estimation

Reduced-state sequence estimation (RSSE) is a suboptimal modification of the Viterbi algorithm (VA) which reduces the computational complexity of maximum likelihood sequence estimation. However, the maximum achievable throughput of RSSE may be significantly lower than the VA, as in addition to the add-compare-select function the critical path comprises branch metric computation, survivor memory operations, and decision-feedback calculation, This paper shows that precomputation of branch metrics can shorten the critical path of RSSE such that its delay becomes of the same order as the VA.

The use of reduced two's-complement representation in low-power DSP design

Twos complement signal representation is widely used in the implementation of arithmetic operations. However, it is well-known that its sign-extension can cause undesirable signal transitions in the MSBs of a data-path circuit. We propose a novel technique to reduce the signal transitions due to sign-extension while retaining the simplicity of the twos complement arithmetic operations. The key idea is to generate a signal representation dynamically according to the signal magnitude. This paper discusses the implementation techniques of using reduced representation in data-path designs. We have applied our proposed techniques in several design examples and our experimental results have shown 13% to 32% power reductions.

Class-F power amplifier with 80.1% maximum PAE at 2 GHz for cellular base-station applications

A GaN HEMT class-F power amplifier (PA) achieving a high maximum power added efficiency (PAE) is presented. The class-F PA exhibits maximum PAE of 80.1 % with an output power of 40.7 dBm at 2 GHz. The PA maintains PAE higher than 50% at 6-dB input back off. The PA shows PAE higher than 70% over 200-MHz frequency range from 1.9 GHz to 2.1 GHz. Source-pull and load-pull techniques in largesignal analysis were conducted to achieve optimum impedance terminations at fundamental and harmonics.

Electrical backplane equalization using programmable analog zeros and folded active inductors

In this paper, we present a low-power small-area electrical backplane equalizer using programmable analog zeros and folded active inductors. We also present a dc-offset cancellation circuit, which occupies less chip area than the traditional offset cancellation schemes. The equalizer circuit was fabricated in a 1.0-V 90-nm CMOS process. With one zero stage, the equalizer occupies 0.015-mm2 chip area and dissipates 12 mW of power. At 4.25-Gb/s data rate, the equalizer provides 7.8-dB gain boost at the Nyquist frequency. Without the use of any transmitter equalization, the analog zero equalizer demonstrated error-free transmission for pseudorandom-bit-sequence-31 data patterns over 34-in lossy FR4 backplanes.

Reduced-state sequence estimation with tap-selectable decision-feedback

Reduced-state sequence estimation (RSSE) with tap-selectable decision-feedback is presented which significantly reduces the computational complexity of RSSE for sparse postcursor impulse response channels. Prefiltering is considered for more general channels, where a few channel coefficients constitute a large portion of the overall channel energy. Tap-selectable RSSE is less computationally expensive and better suited for high-speed VLSI implementation than prior reduced complexity RSSE techniques.

Linearization and Imbalance Correction Techniques for Broadband Outphasing Power Amplifiers

This paper presents adaptive phase-only memory digital pre-distortion (DPD) and gain/phase/delay imbalance correction techniques for outphasing power amplifiers (PAs). Least squares adaptation is used for the phase-only DPD and imbalance correction techniques. The performance of these techniques is verified by co-simulations and measurements of an outphasing PA implemented with two identical class-F PAs and a Chireix combiner. The Chireix combiner with compensating stubs added to achieve high efficiency introduces nonlinearity. The proposed adaptive phase-only memory DPD corrects for the nonlinearity due to the Chireix combiner. The proposed gain/phase/delay imbalance correction technique achieves total lower/upper adjacent channel power ratio (ACPR) improvements of 43.8/37.6 dB for 5-MHz and 46.2/38.3 dB for 10-MHz long-term-evolution signals in measurements. The fractional-sample delay imbalance correction reduces distortion at low input amplitudes and demonstrates on the order of a 10-dB ACPR improvement compared to full-sample delay imbalance correction.

Pipelined reduced-state sequence estimation

The throughput of reduced-state sequence estimation (RSSE) is limited by a substantially longer recursive loop than the add-compare-select function, which is the bottleneck of Viterbi decoding. This paper reformulates the RSSE algorithm to allow pipelining of the branch metric and decision-feedback computation. With this approach the critical path is shortened to the order of the add-compare-select function with only modest increase in hardware.

Characterization of Class-F Power Amplifier With Wide Amplitude and Phase Bandwidth for Outphasing Architecture

A 2.14 GHz gallium nitride class-F power amplifier (PA) achieving both high efficiency and phase linearity over a wide frequency range is presented. The broadband PA is designed as one channel of outphasing architecture in cellular base-stations and analyzed in amplitude and phase domains. In amplitude domain, the PA exhibits measured maximum power added efficiency (PAE) of 80.1% with an output power of 40.7 dBm at 2 GHz. The PA achieves PAE higher than 55% over 500 MHz frequency range. The optimum second-harmonic load impedance enables the broadband operation. In phase domain, phase linearity of the PA is characterized by using phase modulation signals derived from single-carrier 10 MHz, two-carrier 40 MHz, and two-carrier 60 MHz long term evolution signals with 6.5 dB peak-to-average power ratio.