Kangsheng Chen

A Low-Power Memory-Efficient Resampling Architecture for Particle Filters

In this paper, we propose a compact threshold-based resampling algorithm and architecture for efficient hardware implementation of particle filters (PFs). By using a simple threshold-based scheme, this resampling algorithm can reduce the complexity of hardware implementation and power consumption. Simulation results indicate that this algorithm has approximately equal performance with the traditional systematic resampling (SR) algorithm when the root-mean-square error (RMSE) and lost track are considered. Experimental comparison of the proposed hardware architecture with those based on the SR and the residual systematic resampling (RSR) algorithms was conducted on a Xilinx Virtex-II Pro field programmable gate array (FPGA) platform in the bearings-only tracking context, and the results establish the superiority of the proposed architecture in terms of high memory efficiency, low power consumption, and low latency.

Novel Roughening Algorithm and Hardware Architecture for Bearings-Only Tracking Using Particle Filter

In the bearings-only tracking problem, usually the uncertainty of process model is small compared with the uncertainty of measurement and this will lead to severe sample impoverishment when using particle filter (PF). In this paper, we proposed a novel roughening algorithm and its hardware architecture to solve this problem. The reasonable distribution of the roughening jitter is calculated from the innovations related to the survived particles. Simulation results indicate that for the bearings-only tracking problem, the PF with the proposed roughening algorithm outperforms the general PF and the PF with the typical roughening algorithm. Experimental study indicates that this roughening algorithm can be efficiently implemented in hardware and can effectively solve the bearings-only tracking problem with fast processing rate and low complexity.

Easy-hardware-implementation MMPF for Maneuvering Target Tracking: Algorithm and Architecture

In this paper, we present an easy-hardware-implementation multiple model particle filter (MMPF) for maneuvering target tracking. In the proposed filter, the sampling importance resampling (SIR) filter typically used for nonlinear and/or non-Gaussian application is extended to incorporating multiple models that are composed of a constant velocity (CV) model and a “current” statistical (CS) model, and the Independent Metropolis Hasting (IMH) sampler is utilized for the resampling unit in each model. Compared with the bootstrap MMPF, the proposed MMPF requires no knowledge of models and model transition probabilities for different maneuvering motions, and keeps a constant number of particles per model at all times. This allows a regular pipelined hardware structure and can be implemented in hardware easily. Furthermore, using the IMH sampler for the resampling unit avoids the bottleneck introduced by the traditional systematic resampler and reduces the latency of the whole implementation. Simulation results indicate that the proposed filter has approximately equal tracking performance with the bootstrap MMPF. Hardware architecture of the IMH sampler and its corresponding sample unit are presented, and a parallel architecture consisting of CV model processing element (PE), CS model PE and a central unit (CU) is described. The proposed architecture is evaluated on a Xilinx Virtex-II Pro FPGA platform for a maneuvering target tracking application and the results show many advantages of the proposed MMPF over existing approaches in terms of efficiency, lower latency, and easy hardware implementation.

Novel multiple-model probability hypothesis density filter for multiple maneuvering targets tracking

In this paper, we present a novel multiple-model probability hypothesis density (MMPHD) filter for multiple maneuvering targets tracking. In the proposed MMPHD filter, the multiple models are composed of two models, namely a constant velocity (CV) model and a “current” statistical (CS) model, and the PHD is approximated by a set of weighted random samples propagated over time using sequential Monte Carlo (SMC) methods. This resulting filter requires no knowledge of models and model transition probabilities for different maneuvering motions. Simulation results demonstrate that compared with the standard MMPHD filter, the proposed filter shows similar tracking performances but has faster processing rate.

Adaptive Regularized Particle Filter for Synchronization of Chaotic Colpitts Circuits in an AWGN Channel

For chaotic trajectories, when the system parameters are fixed, they are generally confined in a bounded state space. In this paper, we propose an adaptive regularized particle filter (RPF), which makes the best of this inherent characteristic, for identical synchronization of chaotic Colpitts circuits combating additive white Gaussian noise (AWGN) channel distortion. This proposed filter incorporates RPF that resamples from a continuous approximation of the posterior density to avoid sample impoverishment and then utilizes the revised Kullback–Leibler distance (KLD) sampling to adaptively select the number of particles used. Compared with the existing particle filters (PFs) with fixed large number of particles, this proposed adaptive RPF propagates less number of particles with similar performance and thus provides a much more efficient solution for this problem.

Current statistical model probability hypothesis density filter for multiple maneuvering targets tracking

The probability hypothesis density (PHD) filter, which propagates only the first moment (or PHD) instead of the full target posterior, has been shown to be a computationally efficient solution to multi-target tracking problems. Incorporating the current statistical model that is effective in dealing with the maneuvering motions, this paper proposes a current statistical model PHD (CSMPHD) filter for multiple maneuvering targets tracking. This proposed filter approximates the PHD by a set of weighted random samples propagated over time based on the current statistical model using sequential Monte Carlo (SMC) methods. Simulation results demonstrate that the proposed filter shows similar performances with the multiple-model PHD (MMPHD) filter, but it avoids the difficulty of model selection for maneuvering targets and has faster processing rate.

Intermediate frequency circuit design for a 60GHz LFMCW radar

This paper describes an intermediate frequency (IF) circuit design in a 60GHz linear frequency-modulated continuous-wave (LFMCW) radar system. The IF circuit includes a preamplifier stage, an auto-gain amplifier stage and an analog-to-digital (ADC) stage. Totally the IF circuit has a gain of more than 120dB, which helps the system to have the ability of detecting target with distance of 150m. The details of the IF circuit design are presented and the experimental results of the whole radar prototyping system are given.

Compact resampling algorithm and hardware architecture for paticle filters

In this paper, we propose a compact threshold-based resampling algorithm and architecture for efficient hardware implementation of particle filters. By using a simple threshold-based scheme and assigning each particle a weight independent of its previous value, this resampling algorithm can reduce the complexity of hardware implementation. Simulation results from Matlab indicate that this algorithm has approximately equal performance with the traditional systematic resampling (SR) algorithm when the RMSE is considered. Compact hardware architecture for resampling is presented and the bearings-only tracking problem is used for illustration and evaluation. Experimental study on a Xilinx Virtex 2 pro FPGA platform shows that this hardware architecture is efficient in terms of resource usage and latency.

A 60GHz voltage-controlled oscillator with a 3.6GHz tuning range in 180nm CMOS technology

The unlicensed band around 60GHz has been allocated for wireless communications at data rates of several gigabits per second, consequently the high speed transceivers operating at 60GHz is receiving significant research interest. This paper presents a 60GHz voltage-controlled oscillator using linear superposition technique in SMIC 0.18µm CMOS technology. This technique demonstrates the design feasibility for an oscillator whose output frequency is much higher than the device fmax. The proposed circuit consists of a quadrature voltage-controlled oscillator (QVCO) and a transconductance stage. The circuit exhibits a wide tuning range of 3.6GHz and a phase noise of −85 dBc/Hz at 1MHz offset within the entire frequency range while consuming 30.8 mW power from a 1.4V supply voltage. The output power with a 50Ω load is about −33 dBm without an output amplifier. In the real system, the output load should be replaced by 50–100fF capacitive load and the output power can reach about −20 dBm. The circuit occupies a core area of 650×700 µm2.

New real-time resampling algorithm for particle filters

Two kinds of real-time resampling algorithms, local selection (LS) and Markov Chain Monte Carlo (MCMC), are briefly reviewed, and a new resampling algorithm suitable for real-time implementation of particle filters is proposed. The new resampling algorithm incorporates the concept of interleaving to overcome the drawback that when particles with large weights gather together, the performance will be degraded. The proposed resampling algorithm allows pipelined processing and parallelization implementation, which makes the particle filters more efficient. Simulations of a 2D target tracking application are conducted and the results indicate that the tracking accuracy of the proposed algorithm is superior to LS and MCMC. The hardware architecture of the algorithm is given. The hardware complexity including execution time and parallelization is analyzed, and it proves that the proposed method is efficient for real-time application.