Kanji Hirabayashi

Test generation by activation and defect-drive (TEGAD)

Abstract This paper describes an efficient test generation method based on activation and defect-drive using random patterns. The activation process generates patterns to control any circuit node to 0 and 1. After the activation process, the defect-drive propagates the faulted signal, step by step, towards the external output by using parallel fault simulation. The applications are discussed for several gate arrays and micro-processors. The computer run time for the test generation was observed to be proportional to the number of nodes to the power of 1.7 in the case of bit-slice microprocessors. The improvement in manual patterns by the addition of the generated ones was also demonstrated.

Self-checking CMOS circuits using pass-transistor logic

This article presents a new approach to implementing self-checking circuits in CMOS technology. Implementations are made self-checking with respect to a single line stuck-at 0/1 fault. It is assumed that stuck faults at a common gate of neighboring PMOS and NMOS are not independent and the contact between a PMOS (NMOS) source and a power (ground) line is fault free. Self-checking error checkers for parity, two-rail code, and m-out-of-n code are designed using pass-transistor logic and then verified by fault simulation.

A LOW‐ENERGY ELECTRON DIFFRACTION STUDY OF THE EPITAXIAL SILICON LAYERS ON A Ge(111) SURFACE

Silicon atoms were evaporated onto cleaned and annealed Ge(111) surfaces at a rate of 2 × 1014 atoms/cm2 min up to 40 min. Analyses of LEED patterns have revealed, on the substrate at 870°K, truncated tetrahedra consisting of reconstructed {311} and (111) planes, which have a 3 × 1 and a 7 × 7 superstructure, respectively. The 3 × 1 superstructure was observed on cleaned and annealed Si(311) surfaces in an independent experiment.

Interface states in nitrogen incorporated gate oxides

In this letter, we calculate the interface state energy in nitrogen incorporated gate oxides by using a one‐dimensional two‐band model and Penn’s model connecting the refractive index with typical band gap. We estimate the number of dangling bonds which we consider to be the origin of the interface states by the minimization of the free energy. The calculated results seem to explain qualitatively the recent experimental data on NO annealed oxides.

Probabilistic fault grading based on activation checking and observability analysis

A simplified probabilistic fault grading method is described. The concept of propagation probability is introduced in place of the sensitization probability of STAFAN, and the empirical parameters of STAFAN are eliminated. The division of input vectors into subsets is monitored by the activation or toggle rate. The accuracy of the method is examined for fault coverage estimation and for predicting the undetected faults.

An Algebraic Approach to Formal Verification of Microprocessors

In this letter we report the formal verification of microprocessors. After we describe algebraically a bit-sliced microprocessor at both function and logic levels, we apply the symbolic manipulation of Mathematica.

A Method of Formal Verification of Cryptographic Circuits

In this letter we report the formal verification of encryption and decryption circuits. After we describe algebraically a simple modular arithmetic circuit at both function and logic levels, we apply the symbolic manipulation of Mathematica.

Delay fault simulation of sequential circuits

This article proposes a 7-valued logic appropriate for test generation and fault simulation, in the area of robust tests for gate delay faults, and a straightforward simulation strategy for sequential circuits. It is shown that a purely qualitative logic of robust testing is inadequate for circuits with edge-triggered flip-flops. The relation between the 7-valued logic and the similar logic proposed before by Smith, Schulz et al., and Lin and Reddy are discussed.

Delay fault simulation of self-checking error checkers

A robustly-tested gate-delay fault model is proposed using 7-valued logic, and applied to the delay fault simulation of self-checking error checkers. The simulated results are compared with those obtained using either a nonrobustly-tested gate-delay fault model or a path-delay fault model. Experiments show that the robustly-tested gate-delay fault model gives the most pessimistic evaluation for delay test effectiveness. The CMOS pass transistor logic implementation of the self-checking error checkers is discussed.<<ETX>>

Hazard simulation of sequential circuits

A 7-valued logic appropriate for hazard simulation of sequential circuits is investigated in this letter. The 5-valued system of Lin and Reddy is extended to discriminate transitions with and without hazard. We assume that hazards are damped in the feed-back loop of flip-flops, and introduce a kind of filter to assure it. The application to hazard checking is demonstrated for counter circuits.